Semiconductor structure including bit line compose of a metal layer and a metal silicide layer and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12396161-B2
Application number	US-202217934703-A
Country	US
Kind code	B2
Filing date	Sep 23, 2022
Priority date	May 17, 2022
Publication date	Aug 19, 2025
Grant date	Aug 19, 2025

Abstract

Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate provided with a plurality trenches arranged at intervals; a bit line at least located on a sidewall of the trench, wherein both the bit line and the trench extend along a first direction; a bit line isolation layer filled in the trench; a plurality of first semiconductor pillars arranged at intervals on a surface of the substrate; a plurality of word lines arranged at intervals, wherein the word lines are separated from the substrate and cover the first semiconductor pillars by a certain height, the word line extends along a second direction, and the second direction is different from the first direction; and a dielectric layer at least located between the first semiconductor pillar and the word line.

First claim

The invention claimed is:

1. A semiconductor structure, comprising:
a substrate provided with a plurality of trenches arranged at intervals;
a bit line at least located on a sidewall of the trench, wherein both the bit line and the trench extend along a first direction;
a bit line isolation layer filled in the trench;
a plurality of first semiconductor pillars arranged at intervals on a surface of the substrate;
a plurality of word lines arranged at intervals, wherein the word lines are separated from the substrate and cover the first semiconductor pillars by a certain height, the word line extends along a second direction, and the second direction is different from the first direction; and
a dielectric layer at least located between the first semiconductor pillar and the word line;
wherein the bit line comprises a metal layer and a metal silicide layer that are in contact with each other and extend along the first direction; and the metal layer is located on the sidewall of the trench, and the metal silicide layer is located in the substrate between adjacent ones of the trenches.

2. The semiconductor structure according to claim 1 , wherein the bit line isolation layer comprises an edge isolation layer and an internal isolation layer, the edge isolation layer covers a bottom sidewall and a bottom surface of the trench, the bit line covers at least a top sidewall of the trench, the edge isolation layer and the bit line enclose an internal trench, and the internal isolation layer is filled in the internal trench.

3. The semiconductor structure according to claim 1 , wherein the first semiconductor pillar comprises a first source-drain region, a channel region, and a second source-drain region that are stacked, and the dielectric layer further covers a sidewall of the channel region and a sidewall of the second source-drain region; and
the word line covers the dielectric layer located in the channel region and exposes the dielectric layer located on the sidewall of the second source-drain region.

4. The semiconductor structure according to claim 1 , wherein the first semiconductor pillar comprises a first source-drain region and a channel region that are stacked, and the dielectric layer covers a sidewall of the channel region; and the word line covers the dielectric layer; and
the semiconductor structure further comprises a plurality of second semiconductor pillars arranged at intervals, located on the first semiconductor pillars, and directly correspond to the first semiconductor pillars respectively, wherein the second semiconductor pillar is used as a second source-drain region.

5. The semiconductor structure according to claim 4 , wherein a cross-sectional area of the second semiconductor pillar is greater than a cross-sectional area of the first semiconductor pillar.

6. A method of manufacturing a semiconductor structure, comprising:
providing a substrate;
forming a plurality of trenches arranged at intervals in the substrate;
forming a bit line at least located a sidewall of the trench, wherein both the bit line and the trench extend along a first direction;
forming a bit line isolation layer filled in the trench;
after forming the bit line isolation layer, forming a plurality of first semiconductor pillars arranged at intervals on a surface of the substrate;
forming a dielectric layer, wherein the dielectric layer covers a sidewall of the first semiconductor pillar by a certain height; and
forming a plurality of word lines arranged at intervals, wherein the word lines are separated from the substrate, the word lines cover the first semiconductor pillars by a certain height and at least a part of the dielectric layer, the word lines extend along a second direction, and the second direction is different from the first direction;
the forming bit lines comprises:
forming a metal layer located on the sidewall of the trench, wherein the metal layer extends along the first direction, and the bit line isolation layer is in contact with the metal layer; and
carrying out a metal silicide process by using formation temperature of the dielectric layer, such that metal atoms in the metal layer diffuse to the substrate between adjacent ones of the trenches to form a metal silicide layer, wherein the metal silicide layer and the metal layer constitute the bit line.

7. The method of manufacturing the semiconductor structure according to claim 6 , wherein
the forming a metal layer and a bit line isolation layer comprises:
forming an initial edge isolation layer on the sidewall of the trench;
forming an internal isolation layer filled in the trench, wherein the internal isolation layer is in contact with the initial edge isolation layer;
removing the initial edge isolation layer located on a top sidewall of the trench, and using the remaining initial edge isolation layer as an edge isolation layer, wherein the edge isolation layer and the internal isolation layer constitute the bit line isolation layer; and
forming the metal layer on the top sidewall of the trench.

8. The method of manufacturing the semiconductor structure according to claim 6 , wherein the forming first semiconductor pillars comprises:
forming a first semiconductor layer covering the substrate; and
performing first patterning processing on the first semiconductor layer to form the first semiconductor pillars arranged at intervals; and
before the forming a dielectric layer, the method of manufacturing the semiconductor structure further comprises: forming a bottom isolation layer, wherein the bottom isolation layer covers a bottom sidewall of the first semiconductor layer.

9. The method of manufacturing the semiconductor structure according to claim 8 , wherein the first patterning processing and the forming a bottom isolation layer comprise:
removing a part of the first semiconductor layer along the first direction to form a plurality of first semiconductor walls arranged at intervals, wherein the first semiconductor wall extends along the first direction and is located on the substrate between adjacent ones of the trenches;
forming a first isolation wall between adjacent ones of the first semiconductor walls;
removing a part of the first semiconductor wall and a part of the first isolation wall along the second direction to form the first semiconductor pillar and a first isolation block, wherein the first semiconductor pillar and the first isolation block are alternately arranged in the second direction;
forming a second isolation wall between the adjacent ones of the first semiconductor pillars and between adjacent first isolation blocks; and
removing the first isolation block and the second isolation wall by a certain height, such that the remaining first isolation block and second isolation wall serve as the bottom isolation layer to cover a bottom sidewall of the first semiconductor pillar.

10. The method of manufacturing the semiconductor structure according to claim 8 , wherein the forming a first semiconductor layer comprises forming a first source-drain film, a channel film, and a second source-drain film that are stacked, wherein the first source-drain film, the channel film, and the second source-drain film constitute the first semiconductor layer;
a first source-drain region, a channel region, and a second source-drain region that are stacked are formed through the first patterning processing, wherein the first source-drain region, the channel region, and the second source-drain region constitute the first semiconductor pillar;
the dielectric layer covers a sidewall of the channel region and a sidewall of the second source-drain region; and
the word line covers the dielectric layer located on the sidewall of

Assignees

• Changxin Memory Tech Inc

Inventors

• Shao Guangsu
• Xiao Deyuan

Classifications

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10B12/488

  Word lines · CPC title

• H10B12/053

  the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383) · CPC title

• H10D30/6728

  Vertical TFTs · CPC title

• H10B12/315

  with the capacitor higher than a bit line · CPC title