Printed circuit board

Patent metadata

Field	Value
Publication number	US-12593403-B2
Application number	US-202318099333-A
Country	US
Kind code	B2
Filing date	Jan 20, 2023
Priority date	Aug 10, 2022
Publication date	Mar 31, 2026
Grant date	Mar 31, 2026

Abstract

A printed circuit board includes a substrate, a first pad and a second pad, respectively disposed on an upper side of the substrate, a first socket disposed in the substrate and including a first circuit, and a first trace disposed in the substrate and disposed between the first and second pads and the first socket with respect to a lamination direction. At least a portion of the first circuit is electrically connected to each of the first and second pads, and is electrically connected to the second pad through a path passing through the first trace.

First claim

What is claimed is:

1 . A printed circuit board comprising:
a substrate; a first pad and a second pad, respectively disposed on an upper side of the substrate; a first socket disposed in the substrate and including a first circuit; a second socket embedded in the substrate and including a second circuit; and a first trace disposed in the substrate and disposed between the first socket and at least one of the first and second pads with respect to a lamination direction of insulating layers of the substrate, wherein at least a portion of the first circuit is connected to each of the first and second pads, and is connected to the second pad through a path passing through the first trace.

2 . The printed circuit board of claim 1 , wherein
the first socket at least partially overlaps the first pad and is spaced apart from the second pad, with respect to the lamination direction.

3 . The printed circuit board of claim 1 , further comprising:
a first semiconductor chip and a second semiconductor chip, respectively disposed on the substrate and respectively connected to the first and second pads, wherein the first socket at least partially overlaps the first semiconductor chip and is spaced apart from the second semiconductor chip, with respect to the lamination direction.

4 . The printed circuit board of claim 1 , further comprising:
a third pad disposed on the upper side of the substrate; a fourth pad disposed on a lower side of the substrate opposing the upper side; and a second trace disposed in the substrate, and disposed between the third and fourth pads in the lamination direction, wherein another portion of the first circuit is connected to each of the third and fourth pads, and is connected to the fourth pads through a path passing through at least the second trace.

5 . The printed circuit board of claim 1 ,
wherein at least a portion of the second circuit is connected to each of the first and second pads, and is connected to the first pad through a path passing through at least the first trace.

6 . The printed circuit board of claim 5 , wherein
the first trace connects at least a portion of the first circuit and at least a portion of the second circuit to each other.

7 . The printed circuit board of claim 5 , wherein
the first and second sockets are disposed on substantially the same level, with respect to the lamination direction.

8 . The printed circuit board of claim 5 , further comprising:
a first semiconductor chip and a second semiconductor chip, respectively disposed on the substrate and respectively connected to the first and second pads, wherein the first socket at least partially overlaps the first semiconductor chip and is spaced apart from the second semiconductor chip, with respect to the lamination direction, and the second socket at least partially overlaps the second semiconductor chip and is spaced apart from the first semiconductor chip, with respect to the lamination direction.

9 . The printed circuit board of claim 5 , further comprising:
a third pad disposed on the upper side of the substrate; a fourth pad disposed on a lower side of the substrate opposing the lower side; and a second trace disposed in the substrate, and disposed between the third and fourth pads with respect to the lamination direction, wherein another portion of the first circuit is connected to each of the third and fourth pads and is connected to a path passing through at least the second trace.

10 . A printed circuit board comprising:
a substrate including insulating layers, a wiring layer, and a via layer; and a first socket embedded in the substrate and including a first circuit, wherein the via layer includes a plurality of first vias and a plurality of second vias, the first socket includes a plurality of first connection pads and a plurality of second connection pads, the plurality of first vias and the plurality of second vias contact the plurality of first connection pads and the plurality of second connection pads, respectively, and an average pitch between the plurality of second connection pads is greater than an average pitch between the plurality of first connection pads.

11 . The printed circuit board of claim 10 , wherein
at least one of the plurality first connection pads and at least one of the plurality of second connection pads are connected to each other through at least a portion of the first circuit.

12 . The printed circuit board of claim 10 , wherein
each of the plurality of second connection pads has an area, larger than an area of each of the plurality of first connection pads.

13 . The printed circuit board of claim 10 , further comprising:
a first semiconductor chip and a second semiconductor chip, respectively mounted on the substrate, wherein the wiring layer includes a trace, at least one of the plurality of first connection pads is connected to the first semiconductor chip through a path passing through at least the plurality of first vias, at least one of the plurality of second connection pads is connected to the trace through a path passing through at least the plurality of second vias, and the trace is connected to the second semiconductor chip.

14 . The printed circuit board of claim 13 , wherein
the wiring layer includes a plurality of first pads and a plurality of second pads, the plurality of first semiconductor chips and the plurality of second semiconductor chips are connected to the plurality of first pads and the plurality of second pads, respectively, and the plurality of first connection pads are disposed to correspond to the plurality of first pads, and the plurality of second connection pads are disposed to not correspond to the plurality of second pads.

15 . The printed circuit board of claim 13 , wherein
at least a portion of the plurality of first connection pads overlap the first semiconductor chip and is spaced apart from the second semiconductor chip, with respect to a lamination direction of the insulating layers of the substrate.

16 . The printed circuit board of claim 10 , further comprising:
a second socket embedded in the substrate and including a second circuit, wherein the via layer further includes a plurality of third vias and a plurality of fourth vias, the second socket includes a plurality of third connection pads and a plurality of fourth connection pads, the plurality of third vias and the plurality of fourth vias contact the plurality of third connection pads and the plurality of fourth connection pads, respectively, and an average pitch between the plurality of fourth connection pads is greater than an average pitch between the plurality of third connection pads.

17 . The printed circuit board of claim 16 , wherein
at least one of the plurality of third connection pads and at least one of the plurality of fourth connection pads are connected to each other through at least a portion of the second circuit.

18 . The printed circuit board of claim 16 , further comprising:
a first semiconductor chip and a second semiconductor chip, respectively mounted on the substrate, the wiring layer includes a trace, at least one of the plurality of first connection pads is connected to the first semiconductor chip through a path passing through at least the first via, at least one of the plurality of second connection pads is connected to the trace through a path passing through at least the second via, at least one of plurality of third connection pads is connected to the se

Assignees

• Samsung Electro Mech

Inventors

• Lee Jin Uk
• Han Youn Gyu
• Lee Jin Won
• Lee Da Yeon
• Lee Yong Duk

Classifications

• H05K1/115

  Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title

• H05K1/181

  associated with surface mounted components · CPC title

• H05K2201/10325

  Sockets, i.e. female type connectors comprising metallic connector elements integrated in, or bonded to a common dielectric support · CPC title

• H01R12/515

  Terminal blocks providing connections to wires or cables · CPC title

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title