Analog-to-digital converting circuit for optimizing dual conversion gain operation and operation method thereof

Patent metadata

Field	Value
Publication number	US-12593151-B2
Application number	US-202418788084-A
Country	US
Kind code	B2
Filing date	Jul 29, 2024
Priority date	Nov 25, 2021
Publication date	Mar 31, 2026
Grant date	Mar 31, 2026

Abstract

Disclosed is a circuit which includes a first amplifier that generates a first output signal by comparing a first pixel signal corresponding to a first conversion gain and a first ramp signal and generates a second output signal by comparing a second pixel signal corresponding to a second conversion gain and a second ramp signal, and a second amplifier that generates a third output signal based on the first output signal and generates a fourth output signal based on the second output signal, the first conversion gain is higher than the second conversion gain, and a first power current of the first amplifier when the first pixel signal and the first ramp signal are compared is different from a second power current of the first amplifier when the second pixel signal and the second ramp signal are compared.

First claim

What is claimed is:

1 . A circuit, comprising:
a first transistor configured to receive a first pixel signal corresponding to a first conversion gain and a second pixel signal corresponding to a second conversion gain; a second transistor configured to receive a first ramp signal and a second ramp signal; a first current source connected with a first source terminal of the first transistor and a second source terminal of the second transistor at a common node, and configured to output a first sub power current; a switch connected with the first source terminal and the second source terminal at the common node; and a second current source connected with the switch, and configured to output a second sub power current, wherein the first conversion gain is higher than the second conversion gain, wherein a first power current of the circuit when the first pixel signal and the first ramp signal are compared is different from a second power current of the circuit when the second pixel signal and the second ramp signal are compared.

2 . The circuit of claim 1 , wherein:
the first transistor is connected between a first node and the common node, and operates in response to the first pixel signal and the second pixel signal, and the second transistor is connected between an output node and the common node, and operates in response to the first ramp signal and the second ramp signal.

3 . The circuit of claim 2 , further comprising:
a third transistor connected between the first node and a power node; and a fourth transistor connected between the output node and the power node, wherein a gate node of the third transistor is connected to the first node, wherein the gate node of the third transistor and a gate node of the fourth transistor are connected to each other.

4 . The circuit of claim 3 , further comprising:
a fifth transistor connected between the gate node of the third transistor and the output node, wherein a gate node of the fifth transistor is connected to the gate node of the fourth transistor.

5 . The circuit of claim 1 , wherein:
the first current source is connected between the common node and a ground node, and the second current source is connected between one end of the switch, which is not connected to the common node, and the ground node.

6 . The circuit of claim 1 , wherein:
the first current source generates the first sub power current, the second current source generates the second sub power current, and the first power current is generated by the switch being turned on, and the first power current is equal to sum of the first sub power current and the second sub power current.

7 . The circuit of claim 6 , wherein the second power current is generated by the switch being turned off, and the second power current is equal to the first sub power current.

8 . The circuit of claim 6 , wherein the switch is turned on, when the first transistor receives the first pixel signal and the second transistor receives the first ramp signal.

9 . An operation method of an amplifier comprising:
receiving a pixel signal, wherein the pixel signal includes a first pixel signal corresponding to a first conversion gain, and a second pixel signal corresponding to a second conversion gain; receiving a ramp signal, wherein the ramp signal includes a first ramp signal and a second ramp signal; comparing the pixel signal and the ramp signal; and generating output signal based on the comparing, wherein: the first conversion gain is higher than the second conversion gain, and a first power current of the amplifier when the first pixel signal and the first ramp signal are compared is different from a second power current of the amplifier when the second pixel signal and the second ramp signal are compared.

10 . The operation method of claim 9 , the amplifier comprising:
a first current source connected between a common node and a ground node, and configured to generate a first sub power current, a second current source of which one end is connected to the ground node, and configured to generated a second sub power current, and a switch connected between the common node, and an opposite end of the second current source.

11 . The operation method of claim 10 , wherein, when the first pixel signal and the first ramp signal are compared, the switch is turned on, and the first power current is equal to a sum of the first sub power current and the second sub power current.

12 . The operation method of claim 10 , wherein, when the second pixel signal and the second ramp signal are compared, the switch is turned off, and the second power current is equal to the first sub power current.

13 . The operation method of claim 10 , wherein the amplifier further comprising:
a first transistor configured to operate in response to the pixel signal; and a second transistor configured to operate in response to the ramp signal, wherein a first source terminal of the first transistor is connected with a second source terminal of the second transistor at the common node.

14 . The operation method of claim 13 , wherein the amplifier further comprising:
a third transistor connected between a first node and a power node; and a fourth transistor connected between an output node and the power node, wherein a gate node of the third transistor is connected to the first node, wherein the gate node of the third transistor and a gate node of the fourth transistor are connected to each other.

15 . The operation method of claim 9 , wherein the comparing the pixel signal and the ramp signal comprises:
comparing a reset signal of the first pixel signal and the first ramp signal in a first operation period; comparing an image signal of the first pixel signal and the first ramp signal in a second operation period; comparing an image signal of the second pixel signal and the second ramp signal in a third operation period; and comparing a reset signal of the second pixel signal and the second ramp signal in a fourth operation period.

16 . The operation method of claim 15 , wherein the second ramp signal is an increasing ramp signal during the third operation period, and an offset of the second ramp signal increases when the third operation period starts.

17 . The operation method of claim 16 , wherein an offset signal of the first ramp signal is increased based on a ratio of the first conversion gain and the second conversion gain when the third operation period starts, and
wherein the second ramp signal is adjusted to increase during the third operation period.

18 . The operation method of claim 9 , wherein the comparing the pixel signal and the ramp signal comprises:
comparing a reset signal of the second pixel signal and the second ramp signal in a first operation period; comparing a reset signal of the first pixel signal and the first ramp signal in a second operation period; comparing an image signal of the first pixel signal and the first ramp signal in a third operation period; and comparing an image signal of the second pixel signal and the second ramp signal in a fourth operation period.

19 . The operation method of claim 18 , wherein the second ramp signal is a decreasing ramp signal during the fourth operation period, and an offset of the second ramp signal decreases when the fourth operation period starts.

20 . The operation method of claim 19 , wherein the offset of the second ramp signal is decreased based on a ratio of the first conversion gain and the

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jun Jaehoon
• Kwon Hyukbin
• Joo Woong

Classifications

• H04N25/709

  Circuitry for control of the power supply · CPC title

• H04N25/616

  involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling · CPC title

• H04N25/59

  by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance · CPC title

• H04N25/778 Primary

  comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself · CPC title

• H04N25/772 Primary

  comprising A/D, V/T, V/F, I/T or I/F converters · CPC title