Efuse unit and application circuit thereof

Patent metadata

Field	Value
Publication number	US-12592292-B2
Application number	US-202418440635-A
Country	US
Kind code	B2
Filing date	Feb 13, 2024
Priority date	Mar 14, 2023
Publication date	Mar 31, 2026
Grant date	Mar 31, 2026

Abstract

The present invention discloses an efuse unit, including a first fuse, a second fuse, a first NMOS, a second NMOS and a third NMOS. One end of the first fuse serves as a Q1 port, and the other end is connected to drain end of the third NMOS and the first NMOS. One end of the second fuse serves as a Q2 port and is short-circuited to a source end of the third NMOS, and the other end is connected to a drain end of the second NMOS. Agate end of the third NMOS serves as an RDWL port. A gate end of the first NMONS serves as a WLC port. A gate end of the second NMOS serves as a WL port. The present invention can improve the correctness of the reading operation, reduce the voltage required for the programming operation, reduce the programming current.

First claim

What is claimed is:

1 . An application circuit of an efuse unit, comprising:
a first P-channel Metal-Oxide-Semiconductor (PMOS) transistor (Mp 1 ), a second PMOS transistor (Mp 2 ) and a Sense Amplifier (SA) module; the efuse unit, comprising a first fuse (link 1 ), a second fuse (link 2 ), a first N-channel Metal-Oxide Semiconductor (NMOS) transistor (Mn 1 ), a second NMOS transistor (Mn 2 ) and a third NMOS transistor (Mn 3 ); one end of the first fuse (link 1 ) serving as a Q1 port of the efuse unit, and the other end being connected to a drain end of the third NMOS transistor (Mn 3 ) and a drain end of the first NMOS transistor (Mn 1 ); one end of the second fuse (link 2 ) serving as a Q2 port of the efuse unit and being short-circuited to a source end of the third NMOS transistor (Mn 3 ), and the other end being connected to a drain end of the second NMOS transistor (Mn 2 ); a source end of the first NMOS transistor (Mn 1 ) and a source end of the second NMOS transistor (Mn 2 ) being connected to the ground; a gate end of the third NMOS transistor (Mn 3 ) serving as a reading operation control signal (RDWL) port of the efuse unit; a gate end of the first NMOS transistor (Mn 1 ) serving as a work line control (WLC) port of the efuse unit; and a gate end of the second NMOS transistor (Mn 2 ) serving as a word line (WL) port of the efuse unit; a drain end (BLA) of the first PMOS transistor (Mp 1 ) being connected to the Q1 port of the efuse unit; a drain end (BLB) of the second PMOS transistor (Mp 2 ) being connected to the Q2 port of the efuse unit; source ends of the first PMOS transistor (Mp 1 ) and the second PMOS transistor (Mp 2 ) being short-circuited to a programming power supply (VDDQ); gate ends of the first PMOS transistor (Mp 1 ) and the second PMOS transistor (Mp 2 ) being short-circuited to a bit line control signal (BLC); and the Q1 port of the efuse unit being connected to the SA module.

2 . The application circuit of an efuse unit according to claim 1 , wherein
the SA module comprises a comparator, a zeroth voltage dividing resistor (R 0 ), a first voltage dividing resistor (R 1 ), a reference resistor (Ref), a fourth NMOS transistor (Mn 4 ), a fifth NMOS transistor (Mn 5 ) and a sixth NMOS transistor (Mn 6 ); a drain end of the sixth NMOS transistor (Mn 6 ) and one end of the first voltage dividing resistor (R 1 ) are short-circuited to a negative input end of the comparator; a source end of the sixth NMOS transistor (Mn 6 ) is connected to the Q1 port of the efuse unit; a drain end of the fifth NMOS transistor (Mn 5 ) and one end of the zeroth voltage dividing resistor (R 0 ) are short-circuited to a positive input end of the comparator; a source end of the fifth NMOS transistor (Mn 5 ) is connected to one end of the reference resistor (Ref), and a gate end is connected to a reading operation signal (RD); a drain end of the fourth NMOS transistor (Mn 4 ) is connected to the other end of the reference resistor (Ref), and a source end is connected to the ground (GND); and a gate end of the fourth NMOS transistor (Mn 4 ), the other end of the first voltage dividing resistor (R 1 ) and the other end of the zeroth voltage dividing resistor (R 0 ) are all connected to a working power supply (VDD).

3 . The application circuit of an efuse unit according to claim 2 , wherein the voltage of the programming power supply (VDDQ) is lower than the voltage of the working power supply (VDD).

4 . The application circuit of an efuse unit according to claim 2 , wherein the resistance of the zeroth voltage divider (R 0 ) and the resistance of the first voltage dividing resistor (R 1 ) are the same.

5 . The application circuit of an efuse unit according to claim 2 , wherein a logical AND operation is performed on a programming operation signal (PR), a reverse of the read operation signal (RD) and a word line selection signal (WL) through an AND gate to output a word line control (WLC) signal to the WLC port of the efuse unit.

6 . The application circuit of an efuse unit according to claim 5 , wherein a logical AND operation is performed on the reading operation signal (RD) and the word line (WL) selection signal through an AND gate to output a reading operation control signal (RDWL) to the RDWL port of the efuse unit.

Assignees

• Shanghai Huali Integrated Circuit Corp

Inventors

• Yan Ying

Classifications

• G11C17/18

  Auxiliary circuits, e.g. for writing into memory · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• G11C17/165

  Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses (digital stores using resistance random access memory elements G11C13/0002) · CPC title