Electronic fuse cell array structure

Patent metadata

Field	Value
Publication number	US-2021125678-A1
Application number	US-202016993380-A
Country	US
Kind code	A1
Filing date	Aug 14, 2020
Priority date	Oct 29, 2019
Publication date	Apr 29, 2021
Grant date	—

Abstract

An eFuse cell array includes a first unit cell and a second unit cell, each including a PN diode, a cell read transistor, and a fuse element. A first placement order of the PN diode, the cell read transistor, and the fuse element in the first unit cell is reversed with respect to a second placement order of the PN diode, the cell read transistor, and the fuse element in the second unit cell.

First claim

What is claimed is:

1 . An eFuse cell array comprising:
a first unit cell and a second unit cell, each comprising: a PN diode; a cell read transistor; and a fuse element, wherein a first placement order of the PN diode, the cell read transistor, and the fuse element in the first unit cell is reversed with respect to a second placement order of the PN diode, the cell read transistor, and the fuse element in the second unit cell.

2 . The eFuse cell array of claim 1 , wherein each of the first unit cell and the second unit cell further comprises:
a write wordline coupled to a cathode of the PN diode; a read wordline coupled to a gate of the cell read transistor; and a bitline coupled to an anode of the fuse element.

3 . The eFuse cell array of claim 1 , wherein in each of the first unit cell and the second unit cell, a source region of the cell read transistor, an anode of the PN diode and a cathode of the fuse element are coupled to each other through a common node.

4 . The eFuse cell array of claim 1 , wherein a position of the PN diode in the first unit cell is diametrically opposed to a position of the PN diode in the second unit cell.

5 . The eFuse cell array of claim 1 , wherein a position of the fuse element in the first unit cell is diametrically opposed to a position of the fuse element in the second unit cell.

6 . The eFuse cell array of claim 1 , further comprising:
a shared read transistor electrically coupled to each of the fuse elements in the first unit cell and the second unit cell, wherein the cell read transistor and the shared read transistor are NMOS transistors.

7 . The eFuse cell array of claim 6 , further comprising:
a shared program transistor electrically coupled to each of the fuse elements in the first unit cell and the second unit cell, wherein the shared program transistor is a PMOS transistor.

8 . The eFuse cell array of claim 7 , wherein each of the fuse elements in the first unit cell and the second unit cell is further electrically coupled to the shared read transistor.

9 . The eFuse cell array of claim 1 , wherein the PN diode comprises:
an N-type doped region in an N-type well region; a P-type doped region in the N-type well region; a trench isolation region surrounding the N-type well region; and a P-type guard ring structure surrounding the trench isolation structure.

10 . The eFuse cell array of claim 9 , wherein the cell read transistor comprises:
a source region and a drain region in a well region; a gate insulating layer and a gate electrode disposed between the source region and the drain region, wherein the source region is electrically coupled to the P-type doped region of the PN diode.

11 . The eFuse cell array of claim 10 , wherein the fuse element comprises:
a Poly-Si layer formed on an isolation region; and a silicide layer formed on the Poly-Si layer, wherein a cathode of the fuse element is electrically coupled to the P-type doped region of the PN diode and the source region of the cell read transistor.

12 . An eFuse cell array comprising:
a write wordline configured for a write operation; a read wordline configured for a read operation; a bitline disposed orthogonally to the write wordline and the read wordline; a PN diode coupled to the write wordline; a cell read transistor coupled to the read wordline; and a fuse element coupled to the bitline.

13 . The eFuse cell array of claim 12 ,
wherein the write wordline is coupled to a cathode of the PN diode, the read wordline is coupled to a gate of the cell read transistor, and the bitline is coupled to an anode of the fuse element.

14 . The eFuse cell array of claim 12 , wherein a source region of the cell read transistor, an anode of the PN diode, and a cathode of the fuse element are coupled to each other through a common node.

15 . The eFuse cell array of claim 12 , further comprising:
a shared read transistor coupled to the fuse element for read operation, wherein a read current flows through the cell read transistor, the fuse element, and the shared read transistor.

16 . The eFuse cell array of claim 15 , further comprising:
a shared program transistor coupled to the fuse element to provide a programming current to the fuse element, wherein the programming current flows through the shared program transistor, the fuse element and the PN diode, such that the programming current has a current path opposite to that of the read current on the fuse.

17 . The eFuse cell array of claim 12 , further comprising:
a sense amplifier configured to determine whether the fuse element is programmed.

18 . The eFuse cell array of claim 12 , further comprising:
a read current supplier configured to provide a read current, wherein the read current supplier comprises: a read current transistor; and a read current resistor coupled to the read current transistor.

19 . The eFuse cell array of claim 18 , further comprising:
a reference voltage supplier configured to supply a reference voltage, wherein the reference voltage supplier comprises:
a first reference transistor corresponding to the read current transistor; and
a first reference resistor corresponding to the read current resistor.

20 . The eFuse cell array of claim 19 , wherein the reference voltage supplier further comprises:
a second reference transistor corresponding to the cell read transistor; a second reference resistor corresponding to the fuse; and a third reference transistor corresponding to the shared read transistor.

21 . The eFuse cell array of claim 12 , wherein the PN diode comprises:
an N-type doped region in an N-type well region; a P-type doped region in the N-type well region; a trench isolation region surrounding the N-type well region; and a P-type guard ring structure surrounding the trench isolation structure.

22 . The eFuse cell array of claim 21 , wherein the cell read transistor comprises:
a source region and a drain region in a well region; a gate insulating layer and a gate electrode disposed between the source region and the drain region, wherein the source region is electrically coupled to the P-type doped region of the PN diode.

23 . The eFuse cell array of claim 22 , wherein the fuse element comprises:
a Poly-Si layer formed on an isolation region; and a silicide layer formed on the Poly-Si layer, wherein a cathode of the fuse element is electrically coupled to the P-type doped region of the PN diode and the source region of the cell read transistor.

24 . The eFuse cell array of claim 12 , further comprising:
a wordline driver configured to select one of wordlines in the cell array; a program driver configured to provide a programming current to the fuse; and a control logic configured to control the wordline driver and the program driver.

25 . An eFuse cell array comprising:
a memory element coupled to a bitline; a diode configured to couple the memory element to a write wordline; a cell read transistor coupled to the memory element and a gate of the cell read transistor coupled to a read wordline; a shared read transistor configured to couple the memory element through the bitline to a ground; and a shared program transistor coupled to the memory element through the bitline.

26 . The eFuse cell array of claim 25 , further comprising a common node to which a sourc

Assignees

• Key Foundry Co Ltd

Inventors

• Cho Jong Min
• Park Sung Bum
• Ahn Kee Sik
• Park Seong Jun

Classifications

• H10W20/493

  Fuses, i.e. interconnections changeable from conductive to non-conductive · CPC title

• H10W20/491

  Antifuses, i.e. interconnections changeable from non-conductive to conductive · CPC title

• H10B20/25

  One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links · CPC title

• G11C17/18 Primary

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C17/165

  Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses (digital stores using resistance random access memory elements G11C13/0002) · CPC title