Multiplexed display panel preventing surface noise generated during switching of switching transistor, multiplexed display device, and driving method for multiplexed display panel

Patent metadata

Field	Value
Publication number	US-12592209-B2
Application number	US-202418959687-A
Country	US
Kind code	B2
Filing date	Nov 26, 2024
Priority date	Dec 16, 2021
Publication date	Mar 31, 2026
Grant date	Mar 31, 2026

Abstract

A multiplexed display panel includes sub-pixels, gate line, data lines, and a demultiplexer. The demultiplexer includes input channels each provided with switching transistors and fanout lines. Each fanout line is correspondingly connected to one data line by one switching transistor to provide one data signal to the one data line. The one switching transistor corresponding to each input channel is controlled by a same control signal. While each gate line scans one row of the sub-pixels, when a rising edge of the control signal reaches an amplitude, and at a moment when the one switching transistor is controlled by the control signal to be on, the demultiplexer is configured to make a difference between a potential reached by a rising edge of one fanout line correspondingly connected to the one data line and a potential of the one data line to be less than a preset threshold.

First claim

What is claimed is:

1 . A multiplexed display panel, comprising:
a plurality of sub-pixels arranged in an array; a plurality of gate lines configured to scan a plurality of rows of the plurality of sub-pixels; a plurality of data lines configured to input data signals to a plurality of columns of the plurality of sub-pixels; and a demultiplexer comprising a plurality of input channels configured to provide the data signals to the plurality of data lines, wherein each of the plurality of input channels is provided with a plurality of switching transistors and a plurality of fanout lines, each of the plurality of fanout lines is correspondingly connected to one data line of the plurality of data lines by one switching transistor of the plurality of switching transistors to provide one data signal of the data signals to the one data line, and the one switching transistor corresponding to each of the plurality of input channels is controlled by a same control signal to be switched on and switched off; and wherein while each of the plurality of gate lines scans one row of the plurality of sub-pixels, and when a rising edge of the control signal reaches an amplitude and at a moment when the one switching transistor corresponding to each of the plurality of input channels is controlled to be switched on by the control signal, the demultiplexer is configured to make a difference between a potential reached by a rising edge of one fanout line of the plurality of fanout lines correspondingly connected to the one data line and a potential of the one data line to be less than a preset threshold.

2 . The multiplexed display panel of claim 1 , wherein the demultiplexer is further configured to, after a falling edge of the control signal reaches zero (0), adjust the potential of the one fanout line to zero (0) from the potential of the one data line.

3 . The multiplexed display panel of claim 1 , wherein the demultiplexer is further configured to, after a falling edge of the control signal reaches zero (0), adjust a falling edge of the one fanout line to zero (0) before a rising edge of another control signal subsequent to the control signal reaches the amplitude.

4 . The multiplexed display panel of claim 1 , wherein the demultiplexer is configured to, before the rising edge of the control signal reaches the amplitude, adjust the rising edge of the one fanout line from zero (0) to the potential of the one data line in advance.

5 . The multiplexed display panel of claim 1 , wherein the demultiplexer is configured to, before the rising edge of the control signal reaches the amplitude, reduce a duration that the rising edge of the one fanout line reaches the potential of the one data line from zero (0).

6 . The multiplexed display panel of claim 5 , wherein the duration that the rising edge of the one fanout line reaches the potential of the one data line from zero (0) ranges from 0.6 μs to 0.8 μs.

7 . The multiplexed display panel of claim 1 , wherein the demultiplexer is configured to prolong a duration that the rising edge of the control signal reaches the amplitude from zero (0).

8 . The multiplexed display panel of claim 7 , wherein the duration that the rising edge of the control signal reaches the amplitude from zero (0) ranges from 0.3 μs to 0.4 μs.

9 . The multiplexed display panel of claim 1 , further comprising a source driving module, wherein the demultiplexer is configured to control a potential and timing of each of the data signals by the source driving module.

10 . The multiplexed display panel of claim 1 , wherein the preset threshold is 0.1 V.

11 . A multiplexed display device, comprising the multiplexed display panel, and the multiplexed display panel comprising:
a plurality of sub-pixels arranged in an array; a plurality of gate lines configured to scan a plurality of rows of the plurality of sub-pixels; a plurality of data lines configured to input data signals to a plurality of columns of the plurality of sub-pixels; and a demultiplexer comprising a plurality of input channels configured to provide the data signals to the plurality of data lines, wherein each of the plurality of input channels is provided with a plurality of switching transistors and a plurality of fanout lines, each of the plurality of fanout lines is correspondingly connected to one data line of the plurality of data lines by one switching transistor of the plurality of switching transistors to provide one data signal of the data signals to the one data line, and the one switching transistor corresponding to each of the plurality of input channels is controlled by a same control signal to be switched on and switched off; and wherein while each of the plurality of gate lines scans one row of the plurality of sub-pixels, and when a rising edge of the control signal reaches an amplitude and at a moment when the one switching transistor corresponding to each of the plurality of input channels is controlled to be switched on by the control signal, the demultiplexer is configured to make a difference between a potential reached by a rising edge of one fanout line of the plurality of fanout lines correspondingly connected to the one data line and a potential of the one data line to be less than a preset threshold.

12 . A driving method for a multiplexed display panel, the multiplexed display panel comprising:
a plurality of sub-pixels arranged in an array; a plurality of gate lines configured to scan a plurality of rows of the plurality of sub-pixels; a plurality of data lines configured to input data signals to a plurality of columns of the plurality of sub-pixels; and a demultiplexer comprising a plurality of input channels configured to provide the data signals to the plurality of data lines, wherein each of the plurality of input channels is provided with a plurality of switching transistors and a plurality of fanout lines, each of the plurality of fanout lines is correspondingly connected to one data line of the plurality of data lines by one switching transistor of the plurality of switching transistors to provide one data signal of the data signals to the one data line, and the one switching transistor corresponding to each of the plurality of input channels is controlled by a same control signal to be switched on and switched off; and wherein the driving method comprises steps of: scanning the plurality of sub-pixels row by row via the plurality of gate lines; and while each of the plurality of gate lines scans one row of the plurality of sub-pixels, and when a rising edge of the control signal reaches an amplitude and at a moment when the one switching transistor corresponding to each of the plurality of input channels is controlled to be switched on by the control signal, making a difference between a potential reached by a rising edge of one fanout line of the plurality of fanout lines correspondingly connected to the one data line and a potential of the one data line to be less than a preset threshold.

13 . The driving method for the multiplexed display panel of claim 12 , wherein the driving method further comprises the step:
after a falling edge of the control signal reaches zero (0), adjusting the potential of the one fanout line from the potential of the one data line via the demultiplexer.

14 . The driving method for the multiplexed display panel of claim 12 , wherein the driving method further comprises the step:
after a falling edge of the control signal reaches zero (0), adjusting a falling edge of the one fanout line to zero (0) via the demultiplexer before a rising edge of another control signal subsequent to

Assignees

• Wuhan China Star Optoelectronics Technology Co Ltd

Inventors

• Tao Jian
• Feng Shuai
• Li Yafeng
• Peng Zhong
• He Jian

Classifications

• G09G2310/0297

  Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title

• G09G3/3688 Primary

  suitable for active matrices only · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title