Multiplexed display panel preventing surface noise generated during switching of switching transistor, multiplexed display device and driving method for multiplexed display panel

Patent metadata

Field	Value
Publication number	US-12183300-B2
Application number	US-202117623328-A
Country	US
Kind code	B2
Filing date	Dec 20, 2021
Priority date	Dec 16, 2021
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

A multiplexed display panel and device and a driving method for the multiplexed display panel are provided. At the moment when a switching switch is turned on, a potential of a fanout line corresponding to a data line connected to sub-pixels, into which an data signal is input, is adjusted to the same level as a potential of the data line as much as possible, and a potential difference between each fanout line and the corresponding data line is relatively small at the moment when the switching switch is turned on, so that an instantaneous current at this moment is greatly reduced without causing relatively large jump of the potential of the data line, a common electrode and back-plated indium tin oxide (ITO) greatly fluctuate, and then the surface noise generated by the display panel is turned on is greatly reduced.

First claim

What is claimed is:

1. A multiplexed display panel, comprising:
a plurality of sub-pixels, arranged in an array;
a plurality of gate lines, configured to scan a plurality of rows of the plurality of sub-pixels;
a plurality of data lines, configured to input data signals to a plurality of columns of the sub-pixels; and
a demultiplexer, comprising a plurality of input channels configured to provide the data signals to the plurality of data lines,
wherein each of the plurality of input channels is provided with a plurality of switching transistors and a plurality of fanout lines, a source of each of the plurality of switching transistors is correspondingly connected to one of the plurality of fanout lines, a drain of each of the plurality of switching transistors is correspondingly connected one of the plurality of data lines, and one switching transistor of the plurality of switching transistors corresponding to each of the plurality of input channels is controlled to be on/off by a same control signal applied through a gate, and each of the plurality of input channels provides one of the data signals to a corresponding one of the plurality of data lines via a corresponding one of the plurality of fanout lines; and
wherein while each of the plurality of gate lines scans one row of the plurality of sub-pixels, and when a rising edge of the control signal reaches an amplitude and at a moment when the one switching transistor of the plurality of switching transistors corresponding to each of the plurality of input channels is controlled to be on by the control signal, the demultiplexer is configured to make a difference between a potential reached by a rising edge of a corresponding one of the data signals of the corresponding one of the plurality of fanout lines connected to the one switching transistor and a potential of the corresponding one of the plurality of data lines connected to the one switching transistor to be less than a preset threshold.

2. The multiplexed display panel as claimed in claim 1 , wherein the demultiplexer is further configured to, after a falling edge of the control signal reaches zero (0), adjust the potential of the corresponding one of the plurality of fanout lines connected to the one switching transistor to zero (0) from the potential of the corresponding one of the plurality of data lines connected to the one switching transistor.

3. The multiplexed display panel as claimed in claim 1 , wherein the demultiplexer is further configured to, after a falling edge of the control signal reaches zero (0), adjust a falling edge of the corresponding one of the plurality of fanout lines connected to the one switching transistor to zero (0) before a rising edge of another control signal subsequent to the control signal reaches the amplitude.

4. The multiplexed display panel as claimed in claim 1 , wherein the demultiplexer is specifically configured to, before the rising edge of the control signal reaches the amplitude, adjust the rising edge of the corresponding one of the plurality of fanout lines connected to the one switching transistor from zero (0) to the potential of the corresponding one of the plurality of data lines connected to the one switching transistor in advance.

5. The multiplexed display panel as claimed in claim 1 , wherein the demultiplexer is configured to, before the rising edge of the control signal reaches the amplitude, reduce a duration that the rising edge of the corresponding one of the plurality of fanout lines connected to the one switching transistor reaches the potential of the corresponding one of the plurality of data lines connected to the one switching transistor from zero (0).

6. The multiplexed display panel as claimed in claim 5 , wherein the duration that the rising edge of the corresponding one of the plurality of fanout lines connected to the one switching transistor reaches the potential of the corresponding one of the plurality of data lines connected to the one switching transistor from zero (0) ranges from 0.6 μs to 0.8 μs.

7. The multiplexed display panel as claimed in claim 1 , wherein the demultiplexer is configured to prolong a duration that the rising edge of the control signal reaches the amplitude from zero (0).

8. The multiplexed display panel as claimed in claim 7 , wherein the duration that the rising edge of the control signal reaches the amplitude from zero (0) ranges from 0.3 μs to 0.4 μs.

9. The multiplexed display panel as claimed in claim 1 , further comprising a source driving module, wherein the demultiplexer is configured to control a potential and timing of each of the data signals output to the corresponding one of the data lines through the source driving module.

10. The multiplexed display panel as claimed in claim 1 , wherein the preset threshold is 0.1 V.

11. A multiplexed display device, comprising the multiplexed display panel, and the multiplexed display panel comprising:
a plurality of sub-pixels, arranged in an array;
a plurality of gate lines, configured to scan a plurality of rows of the plurality of sub-pixels;
a plurality of data lines, configured to input data signals to a plurality of columns of the plurality of sub-pixels; and
a demultiplexer, comprising a plurality of input channels configured to provide the data signals to the plurality of data lines,
wherein each of the plurality of input channels is provided with a plurality of switching transistors and a plurality of fanout lines, a source of each of the plurality of switching transistors is correspondingly connected to one of the plurality of fanout lines, a drain of each of the plurality of switching transistors is correspondingly connected one of the plurality of data lines, and one switching transistor of the plurality of switching transistors corresponding to each of the plurality of input channels is controlled to be on/off by a same control signal applied through a gate, and each of the plurality of input channels provides one of the data signals to a corresponding one of the plurality of data lines via a corresponding one of the plurality of fanout lines; and
wherein while each of the plurality of gate lines scans one row of the plurality of sub-pixels, and when a rising edge of the control signal reaches an amplitude and at a moment when the one switching transistor of the plurality of switching transistors corresponding to each of the plurality of input channels is controlled to be on by the control signal, the demultiplexer is configured to make a difference between a potential reached by a rising edge of a corresponding one of the data signals of the corresponding one of the plurality of fanout lines connected to the one switching transistor and a potential of the corresponding one of the plurality of data lines connected to the one switching transistor to be less than a preset threshold.

12. A driving method for a multiplexed display panel, the multiplexed display panel comprising:
a plurality of sub-pixels, arranged in an array;
a plurality of gate lines, configured to scan a plurality of rows of the plurality of sub-pixels;
a plurality of data lines, configured to input data signals to a plurality of columns of the plurality of sub-pixels; and
a demultiplexer, comprising a plurality of input channels configured to provide the data signals to the plurality of data lines, wherein each of the plurality of input channels is provided with a plurality of switching transistors and a plurality of fanout lines, a source of each of the plurality of switching transistors is correspondingly connected to one of the plurality of fanout lines, a drain of each of the plurality of switching transistors is correspondingly conne

Assignees

• Wuhan China Star Optoelectronics Technology Co Ltd

Inventors

• Tao Jian
• Feng Shuai
• Li Yafeng
• Peng Zhong
• He Jian

Classifications

• G09G2310/0297

  Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title

• G09G3/3688 Primary

  suitable for active matrices only · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title