User mode direct data access to non-volatile memory express device via kernel-managed queue pair

Patent metadata

Field	Value
Publication number	US-12591536-B2
Application number	US-202418592046-A
Country	US
Kind code	B2
Filing date	Feb 29, 2024
Priority date	Nov 13, 2023
Publication date	Mar 31, 2026
Grant date	Mar 31, 2026

Abstract

Systems and methods are disclosed for implementing a Non-Volatile Memory Express (NVMe) driver in a computer system. The method involves mapping a memory buffer into a user mode address space to facilitate data transfer with an NVMe device via direct memory access (DMA). Additionally, a first NVMe queue pair, including a submission queue (SQ) and a completion queue (CQ), is mapped into the user mode address space, allowing a user mode component to submit commands to the NVMe device. The method further enables the user mode component to ring a doorbell at the NVMe device. Finally, an NVMe command is processed in kernel mode using a second NVMe queue pair comprising a second SQ and a second CQ.

First claim

What is claimed:

1 . A method, implemented by a Non-Volatile Memory Express (NVMe) driver operating in a kernel mode, in a computer system that includes a processor system, comprising:
mapping a memory buffer into a user mode address space, the memory buffer enabling data transfer with an NVMe device via direct memory access (DMA); mapping a first NVMe queue pair, which comprises a first submission queue (SQ) and a first completion queue (CQ), into the user mode address space, the first NVMe queue pair enabling a user mode component to submit a command to the NVMe device; enabling the user mode component to ring a doorbell at the NVMe device, including exposing a system call to the user mode component; and based on receiving the system call from the user mode component,
validating that the user mode component is accessing a valid range of logical block addresses at the NVMe device; and
processing an NVMe command in the kernel mode using a second NVMe queue pair, which comprises a second SQ and a second CQ.

2 . The method of claim 1 , wherein the system call is a first system call, and wherein mapping of the memory buffer into the user mode address space is based on receiving a second system call from the user mode component.

3 . The method of claim 1 , wherein the system call is a first system call, and wherein mapping of the first NVMe queue pair into the user mode address space is based on receiving a second system call from the user mode component.

4 . The method of claim 1 , wherein the system call is a first system call, and wherein enabling of the user mode component to ring the doorbell at the NVMe device is based on receiving a second system call from the user mode component.

5 . The method of claim 1 , wherein the method further comprises, based on receiving the system call from the user mode component, writing a value to an NVMe CQ doorbell.

6 . The method of claim 1 , wherein the method further comprises, based on receiving the system call from the user mode component, writing a value to an NVMe SQ doorbell.

7 . The method of claim 1 , wherein mapping the first NVMe queue pair into the user mode address space comprises at least one of,
mapping a first user mode memory address to the first SQ and mapping a second user mode memory address to the first CQ; or registering a third user mode memory address to the first SQ with an NVMe driver, and registering a fourth user mode memory address to the first CQ with the NVMe driver.

8 . A method, implemented by a user mode component, in a computer system that includes a processor system, comprising:
identifying a mapping of a Non-Volatile Memory Express (NVMe) queue pair, into a user mode address space, the NVMe queue pair comprising a submission queue (SQ) and a completion queue (CQ), and the NVMe queue pair having been mapped into the user mode address space by a kernel mode NVMe driver; submitting an NVMe command to an NVMe device, including,
writing an SQ entry to the SQ of the NVMe queue pair; and
ringing an SQ doorbell register via a system call to the kernel mode NVMe driver, wherein, based on receiving the system call from the user mode component, the kernel mode NVMe driver validates that the user mode component is accessing a valid range of logical block addresses at the NVMe device; and
polling the CQ of the NVMe queue pair and, based on the polling, identifying a CQ entry.

9 . The method of claim 8 , wherein the method further comprises identifying a mapping of a memory buffer into the user mode address space, the memory buffer enabling data transfer with the NVMe device via direct memory access (DMA).

10 . The method of claim 9 , wherein the method further comprises, based on submitting the NVMe command to the NVMe device,
reading first data from the memory buffer, wherein the first data originates from the NVMe device based on the NVMe command; or writing second data to the memory buffer, wherein the second data is written to the NVMe device based on the NVMe command.

11 . The method of claim 8 , wherein calling the system call exposed by the kernel mode NVMe driver results in the kernel mode NVMe driver ringing both of the SQ doorbell register and a CQ doorbell register.

12 . The method of claim 8 , wherein the system call is a first system call, and wherein the method further comprises making a second system call to the kernel mode NVMe driver, which results in the mapping of the NVMe queue pair into the user mode address space.

13 . A computer system, comprising:
a processor system; and a computer storage medium that stores computer-executable instructions that are executable by the processor system to at least:
within a kernel mode context in the computer system:
map a memory buffer into a user mode address space, the memory buffer enabling data transfer with a Non-Volatile Memory Express (NVMe) device via direct memory access (DMA);
map a first NVMe queue pair, which comprises a first submission queue (SQ) and a first completion queue (CQ), into the user mode address space, the first NVMe queue pair enabling a user mode component to submit a command to the NVMe device;
enable the user mode component to ring a doorbell at the NVMe device, including exposing a system call to the user mode component; and
based on receiving the system call from the user mode component,
validate that the user mode component is accessing a valid range of logical block addresses at the NVMe device; and
process a first NVMe command using a second NVMe queue pair, which comprises a second SQ and a second CQ; and

within a user mode context in the computer system:
identify the first NVMe queue pair;
submit a second NVMe command to the NVMe device, including,
writing an SQ entry to the first SQ; and
ringing an SQ doorbell register via the system call; and

poll the first CQ, and, based on the polling, identify a CQ entry.

14 . The computer system of claim 13 , wherein the computer-executable instructions are also executable by the processor system to at least, within the user mode context in the computer system, identify a mapping of the memory buffer into the user mode address space.

15 . The computer system of claim 13 , wherein the system call is a first system call, and wherein mapping of the memory buffer into the user mode address space is based on receiving a second system call from the user mode component.

16 . The computer system of claim 13 , wherein the system call is a first system call, and wherein mapping of the first NVMe queue pair into the user mode address space is based on receiving a second system call from the user mode component.

17 . The computer system of claim 13 , wherein the system call is a first system call, and wherein enabling of the user mode component to ring the doorbell at the NVMe device is based on receiving a second system call from the user mode component.

18 . The computer system of claim 13 , wherein the computer-executable instructions are also executable by the processor system to write a value to an NVMe CQ doorbell based on receiving the system call from the user mode component.

19 . The computer system of claim 13 , wherein the computer-executable instructions are also executable by the processor system to write a value to an NVMe SQ doorbell based on receiving the system call from the user mode component.

20 . The computer system of claim 13 , wherein mapping the first NVMe queue pair into the user mode address space comprises at least one of,
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Assignees

• Microsoft Technology Licensing Llc

Inventors

• Jin Ming
• Makhervaks Vadim
• Dai Ji
• Yan Tengda
• Yi Yuan
• Yin Chuanjun
• Lee Scott Chao-Chueh

Classifications

• G06F13/1673

  using buffers · CPC title

• G06F13/1642 Primary

  with request queuing · CPC title

• G06F2213/1602

  Memory access type · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F13/4072 Primary

  Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002) · CPC title