System and method to extend nvme queues to user space

Patent metadata

Field	Value
Publication number	US-2016306580-A1
Application number	US-201514862145-A
Country	US
Kind code	A1
Filing date	Sep 22, 2015
Priority date	Apr 17, 2015
Publication date	Oct 20, 2016
Grant date	—

Abstract

An embodiment includes a system, comprising: a processor configured to: read a stride parameter from a device coupled to the processor; and map registers associated with the device into virtual memory based on the stride parameter; wherein: the stride parameter is configured to indicate a stride between the registers associated with the device; and the processor is configured to map at least one of the registers to user space virtual memory in response to the stride parameter.

First claim

1 . A system, comprising:
a processor coupled to a processor-local bus and configured to:
read a stride parameter from a device coupled to the processor through the processor-local bus; and
map registers associated with the device into virtual memory based on the stride parameter;
wherein:
the stride parameter is configured to indicate a stride between the registers associated with the device; and
the processor is configured to map at least one of the registers to user space virtual memory in response to the stride parameter.

2 . The system of claim 1 , wherein:
the processor-local bus is a PCI Express (PCIe) bus; the device is an NVMe device; and the registers are doorbell registers associated with queues of the NVMe device.

3 . The system of claim 1 , wherein the stride parameter is set such that at least one register is mapped to kernel space virtual memory.

4 . The system of claim 1 , wherein:
the processor includes a plurality of processing entities; and the processor is configured to map a number of sets of the registers into virtual memory greater than a number of the processing entities.

5 . The system of claim 1 , wherein the stride parameter is set such that a stride between the registers mapped into virtual memory is greater than or equal to a virtual memory page size.

6 . The system of claim 1 , wherein the stride parameter is set such that a stride between the registers mapped into virtual memory is greater than a size of the registers.

7 . The system of claim 6 , wherein the stride parameter is set such that the stride between the registers mapped into virtual memory is less than a virtual memory page size.

8 . The system of claim 1 , wherein the stride parameter is set such that at least two registers are mapped to a single virtual memory page.

9 . The system of claim 1 , wherein:
the processor is configured to present a virtual machine; and at least one register is mapped into virtual memory associated with the virtual machine.

10 . The system of claim 1 , wherein the processor is configured to map the registers into virtual memory such that at least one of the at least one register mapped to user space virtual memory is accessible by a user space application without intervening kernel layers.

11 . A method, comprising:
reading a stride parameter from a device coupled to a processor-local bus, the stride parameter indicating a stride between registers of the device; mapping the registers into virtual memory based on the stride parameter; wherein the stride parameter is set such that at least one register is mapped to user space virtual memory.

12 . The method of claim 11 , wherein mapping the registers comprises mapping a number of the registers into virtual memory greater than a number of processing entities.

13 . The method of claim 11 , wherein mapping the registers comprises mapping the registers such that a stride between the registers in virtual memory is greater than or equal to a virtual memory page size.

14 . The method of claim 11 , wherein mapping the registers comprises mapping the registers such that at least two registers are mapped to a single virtual memory page.

15 . The method of claim 11 , further comprising:
presenting a virtual machine; and wherein mapping the registers comprises mapping at least one register into virtual memory associated with the virtual machine.

16 . A device, comprising:
a memory configured to store data; a plurality of memory mappable registers associated with the memory; and a stride register configured to store a stride parameter indicating a stride of the memory mappable registers; wherein the stride parameter is set such that a separation of the memory mappable registers is non-zero.

17 . The device of claim 16 , wherein:
the device is an NVMe device; and the memory mappable registers are doorbell registers.

18 . The device of claim 16 , wherein the stride parameter is set such that a stride between the registers is greater than or equal to a virtual memory page size.

19 . The device of claim 16 , wherein the stride parameter is set such that a stride between the registers is greater than a size of the registers.

20 . The device of claim 19 , wherein the stride parameter is set such that the stride between the registers is less than a virtual memory page size.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Pinto Oscar Prem

Classifications

• G06F13/4068

  Electrical coupling · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0631 Primary

  by allocating resources to storage systems · CPC title

• G06F3/0665

  at area level, e.g. provisioning of virtual or logical volumes · CPC title