Semiconductor device

Patent metadata

Field	Value
Publication number	US-12588573-B2
Application number	US-202217968496-A
Country	US
Kind code	B2
Filing date	Oct 18, 2022
Priority date	Sep 11, 2020
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

A semiconductor device includes a semiconductor package including an n-type channel normally-off transistor including a first electrode, a second electrode, and a first control electrode, a normally-on transistor including a third electrode electrically connected to the second electrode, a fourth electrode, and a second control electrode, a first diode including a first anode electrically connected to the second control electrode and a first cathode electrically connected to the third electrode, and a Zener diode including a second anode electrically connected to the first electrode and a second cathode electrically connected to the second electrode; a first terminal provided on the semiconductor package, the first terminal being electrically connected to the first electrode; a plurality of second terminals provided on the semiconductor package, the second terminals being electrically connected to the first electrode, and the second terminals being lined up in a first direction; a third terminal provided on the semiconductor package, the third terminal being electrically connected to the fourth electrode; a plurality of fourth terminals provided on the semiconductor package, the fourth terminals being electrically connected to the first control electrode; and a plurality of fifth terminals provided on the semiconductor package, the fifth terminals being electrically connected to the second control electrode, and the fifth terminals being lined up in the first direction.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a semiconductor package including a normally-off transistor, and a normally-on transistor; a fourth terminal provided on the semiconductor package, the fourth terminal being electrically connected to the normally-off transistor; and a fifth terminal provided on the semiconductor package, the fifth terminal being electrically connected to the normally-on transistor, wherein a Kelvin connection is performed to the semiconductor device, wherein parasitic oscillation is suppressed, and wherein a temporal change in voltage due to switching occurred in an unintended form is controlled.

2 . The semiconductor device according to claim 1 , further comprising:
a chip resistor or a chip ferrite bead electrically connected to the fifth terminal.

3 . The semiconductor device according to claim 1 , further comprising:
a first chip diode electrically connected to the fifth terminal; a second chip diode electrically connected to the fifth terminal; and a chip resistor or a chip ferrite bead electrically connected to the second chip diode.

4 . The semiconductor device according to claim 1 , wherein a wiring is electrically connected to the fifth terminal.

5 . The semiconductor device according to claim 1 , wherein a capacitor is electrically connected to the fifth terminal.

6 . The semiconductor device according to claim 5 ,
wherein a resistor is connected to the fourth terminal and the capacitor, and wherein a second diode is electrically connected to the fourth terminal.

7 . The semiconductor device according to claim 1 , further comprising:
a first diode electrically connected to the normally-on transistor.

8 . The semiconductor device according to claim 7 , wherein the semiconductor package further includes the first diode.

9 . The semiconductor device according to claim 7 , wherein the semiconductor device comprises the first diode outside the semiconductor package.

10 . The semiconductor device according to claim 1 , further comprising:
a Zener diode electrically connected to the normally-off transistor or the normally-on transistor.

Assignees

• Toshiba Kk
• Toshiba Electronic Devices & Storage Corp

Inventors

• Sugiyama Toru
• Yoshioka Akira
• Hung Hung
• Isobe Yasuhiro
• Kobayashi Hitoshi
• Ohno Tetsuya
• Hosokawa Naonori
• Onomura Masaaki
• Iwai Masaaki

Classifications

• H10W70/465

  Bumps or wires · CPC title

• H10D30/475

  having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs · CPC title

• H10D8/25

  Zener diodes · CPC title

• H10D1/68

  Capacitors having no potential barriers · CPC title

• H10D1/47

  Resistors having no potential barriers · CPC title