Semiconductor device

Patent metadata

Field	Value
Publication number	US-11508647-B2
Application number	US-202117197107-A
Country	US
Kind code	B2
Filing date	Mar 10, 2021
Priority date	Sep 11, 2020
Publication date	Nov 22, 2022
Grant date	Nov 22, 2022

Abstract

A semiconductor device includes a semiconductor package including an n-type channel normally-off transistor, a normally-on transistor, a first diode, and a Zener diode; a first terminal provided on the semiconductor package; a plurality of second terminals provided on the semiconductor package, and the second terminals being lined up in a first direction; a third terminal provided on the semiconductor package; a plurality of fourth terminals provided on the semiconductor package; and a plurality of fifth terminals provided on the semiconductor package, and the fifth terminals being lined up in the first direction.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor package including
an n-type channel normally-off transistor including a first electrode, a second electrode, and a first control electrode,
a normally-on transistor including a third electrode electrically connected to the second electrode, a fourth electrode, and a second control electrode,
a first diode including a first anode electrically connected to the second control electrode and a first cathode electrically connected to the third electrode, and
a Zener diode including a second anode electrically connected to the first electrode and a second cathode electrically connected to the second electrode;

a first terminal provided on the semiconductor package, the first terminal being electrically connected to the first electrode;
a plurality of second terminals provided on the semiconductor package, the second terminals being electrically connected to the first electrode, and the second terminals being lined up in a first direction;
a third terminal provided on the semiconductor package, the third terminal being electrically connected to the fourth electrode;
a plurality of fourth terminals provided on the semiconductor package, the fourth terminals being electrically connected to the first control electrode; and
a plurality of fifth terminals provided on the semiconductor package, the fifth terminals being electrically connected to the second control electrode, and the fifth terminals being lined up in the first direction.

2. The semiconductor device according to claim 1 , wherein a sixth terminal of a chip resistor or a chip ferrite bead including the sixth terminal and a seventh terminal is electrically connected to any one of the second terminals, and the seventh terminal is electrically connected to any one of the fifth terminals.

3. The semiconductor device according to claim 1 ,
wherein a third cathode of a first chip diode including a third anode and the third cathode is electrically connected to any one of the second terminals,
the third anode is electrically connected to any one of the fifth terminals,
a sixth terminal of a chip resistor or a chip ferrite bead including the sixth terminal and a seventh terminal is electrically connected to any one of the second terminals,
a fourth cathode of a second chip diode including a fourth anode and the fourth cathode is electrically connected to any one of the fifth terminals, and
the seventh terminal and the fourth cathode are electrically connected.

4. The semiconductor device according to claim 1 , wherein any one of the second terminals and any one of the fifth terminals are electrically connected by a wiring.

5. The semiconductor device according to claim 1 , wherein an eighth terminal of a capacitor including the eighth terminal and a ninth terminal is electrically connected to the fifth terminal.

6. The semiconductor device according to claim 5 ,
wherein a tenth terminal of a resistor including the tenth terminal and an eleventh terminal is connected to the fourth terminal,
the eleventh terminal is electrically to the ninth terminal,
a fifth anode of a second diode including the fifth anode and a fifth cathode is electrically to the eleventh terminal,
the fifth cathode is electrically connected to the tenth terminal, and
the second diode is electrically connected in parallel with the resistor.

7. The semiconductor device according co claim 1 , wherein the second terminals and the fifth terminals are provided at an end portion of the semiconductor package.

8. The semiconductor device according to claim 1 , wherein the first terminal, the third terminal, and the fourth terminal are not provided between the second terminals and the fifth terminals.

9. The semiconductor device according to claim 1 , wherein the second terminals are adjacent to the fifth terminals without passing through the first terminal, the third terminal, and the fourth terminal.

10. The semiconductor device according to claim 1 , wherein the first terminal, the third terminal, and the fifth terminal are not provided between the second terminals and the fourth terminals.

11. The semiconductor device according to claim 1 , wherein the second terminals are adjacent to the fourth terminals without passing through the first terminal, the third terminal, and the fifth terminal.

12. A semiconductor device comprising:
a semiconductor package including
a p-type channel normally-off transistor including a first electrode, a second electrode, and a first control electrode,
a normally-on transistor including a third electrode electrically connected to the second electrode, a fourth electrode, and a second control electrode;

at least one first terminal provided on the semiconductor package, the at least one first terminal being electrically connected to the first electrode;
a second terminal provided on the semiconductor package, the second terminal being electrically connected to the second electrode or the third electrode, and the second terminal being lined up in a first direction;
at least one third terminal provided in the semiconductor package, the at least one the third terminal being electrically connected to the fourth electrode;
a fourth terminal provided on the semiconductor package, the fourth terminal being electrically connected to the first control electrode, and the fourth terminal being lined up in the first direction; and
a fifth terminal provided on the semiconductor package, the fifth terminal being electrically connected to the second control electrode, and the fifth terminal being lined up in the first direction.

13. The semiconductor device according to claim 12 , further comprising:
a first diode including a first anode electrically connected to the second control electrode and a first cathode electrically connected to the first electrode.

14. The semiconductor device according to claim 13 , wherein the semiconductor package further includes the first diode.

15. The semiconductor device according to claim 13 , wherein the semiconductor device comprises the first diode outside the semiconductor package.

16. The semiconductor device according to claim 12 , wherein the semiconductor package further includes a Zener diode including a second anode electrically connected to the first electrode and a second cathode electrically connected to the second electrode.

17. The semiconductor device according to claim 12 , wherein the at least one first terminal comprises a plurality of first terminals.

18. The semiconductor device according to claim 12 , wherein the at least one third terminal comprises a plurality of third terminals.

19. The semiconductor device according to claim 12 , wherein the first terminal and the third terminal are provided opposite each other.

20. The semiconductor device according to claim 12 , wherein the semiconductor device further comprises a Zener diode including a second anode electrically connected to the first electrode and a second cathode electrically connected to the second electrode, and the Zener diode is provided outside the semiconductor package.

Assignees

• Toshiba Kk
• Toshiba Electronic Devices & Storage Corp

Inventors

• Sugiyama Toru
• Yoshioka Akira
• Hung Hung
• Isobe Yasuhiro
• Kobayashi Hitoshi
• Ohno Tetsuya
• Hosokawa Naonori
• Onomura Masaaki
• Iwai Masaaki

Classifications

• H10W90/763

  between laterally-adjacent chips · CPC title

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W70/465

  Bumps or wires · CPC title

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title