Semiconductor devices and data storage systems including the same

Patent metadata

Field	Value
Publication number	US-12588516-B2
Application number	US-202318227357-A
Country	US
Kind code	B2
Filing date	Jul 28, 2023
Priority date	Oct 27, 2022
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

A semiconductor device includes a substrate having first and second regions; a first stack structure including lower gate electrodes stacked in a first direction in the first region; a first channel structure penetrating through the first stack structure; a second stack structure on the first stack structure and the first channel structure and including upper gate electrodes stacked in the first direction; a second channel structure penetrating through the second stack structure; a first mold structure including lower horizontal sacrificial layers stacked in the second region; an alignment structure penetrating through the first mold structure; and a second mold structure on the first mold structure and the alignment structure and including upper horizontal sacrificial layers stacked, wherein the number of the lower horizontal sacrificial layers is less than the number of the lower gate electrodes.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a substrate having first and second regions; a first stack structure including lower gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate in the first region; a first channel structure penetrating through the first stack structure and in contact with the substrate; a second stack structure on the first stack structure and the first channel structure and including upper gate electrodes stacked and spaced apart from each other in the first direction; a second channel structure penetrating through the second stack structure and connected to the first channel structure; a first mold structure including lower horizontal sacrificial layers stacked and spaced apart from each other in the first direction in the second region; an alignment structure penetrating through the first mold structure and in contact with the substrate; and a second mold structure on the first mold structure and the alignment structure and including upper horizontal sacrificial layers stacked and spaced apart from each other in the first direction, wherein the number of the lower horizontal sacrificial layers is less than the number of the lower gate electrodes.

2 . The semiconductor device of claim 1 , wherein the lower horizontal sacrificial layers are on substantially the same level as a level of a portion of the lower gate electrodes including a lowermost lower gate electrode.

3 . The semiconductor device of claim 1 , wherein a distance between an uppermost lower gate electrode among the lower gate electrodes and a lowermost upper gate electrode among the upper gate electrodes is less than a distance between an uppermost lower horizontal sacrificial layer among the lower horizontal sacrificial layers and a lowermost upper horizontal sacrificial layer among the upper horizontal sacrificial layers.

4 . The semiconductor device of claim 1 , wherein a lowermost first upper horizontal sacrificial layer among the upper horizontal sacrificial layers contacts a portion of an upper surface and a portion of a side surface of the alignment structure.

5 . The semiconductor device of claim 4 , wherein an upper surface of a second upper horizontal sacrificial layer on the lowermost first upper horizontal sacrificial layer is on a level lower than a level of an upper surface of the alignment structure on a circumference of the alignment structure.

6 . The semiconductor device of claim 4 , wherein a lowermost surface of the lowermost first upper horizontal sacrificial layer is on a level lower than a level of an upper surface of an uppermost lower gate electrode among the lower gate electrodes.

7 . The semiconductor device of claim 1 , wherein the number of the lower horizontal sacrificial layers is 2 to 7 fewer than the number of the lower gate electrodes.

8 . The semiconductor device of claim 1 , wherein the first region is a memory cell region in which memory cells are disposed, and the second region is an alignment key region in which alignment keys are disposed.

9 . The semiconductor device of claim 1 , wherein each of the upper horizontal sacrificial layers has a key pattern portion recessed in an upper surface to correspond to a circumference of the alignment structure.

10 . The semiconductor device of claim 9 ,
wherein the second mold structure further includes interlayer insulating layers alternately stacked with the upper horizontal sacrificial layers, and wherein each of the upper horizontal sacrificial layers and the interlayer insulating layers has the key pattern portion.

11 . The semiconductor device of claim 9 , wherein, in a portion of the upper horizontal sacrificial layers, the key pattern portion has a notch shape.

12 . The semiconductor device of claim 1 , wherein the first channel structure is on substantially the same level as a level of the alignment structure.

13 . The semiconductor device of claim 1 , wherein the alignment structure includes a carbon-based material.

14 . A semiconductor device, comprising:
a substrate having first and second regions; a first stack structure including lower gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate in the first region; a first channel structure penetrating through the first stack structure; a second stack structure on the first stack structure and the first channel structure and including upper gate electrodes stacked and spaced apart from each other in the first direction; a second channel structure penetrating through the second stack structure and connected to the first channel structure; a first mold structure including lower horizontal sacrificial layers stacked and spaced apart from each other in the first direction in the second region; an alignment structure penetrating through the first mold structure; and a second mold structure on the first mold structure and the alignment structure and including upper horizontal sacrificial layers stacked and spaced apart from each other in the first direction, wherein a distance between an uppermost lower gate electrode among the lower gate electrodes and an upper end of the first channel structure is less than a distance between an uppermost lower horizontal sacrificial layer among the lower horizontal sacrificial layers and an upper end of the alignment structure in the first direction.

15 . The semiconductor device of claim 14 , wherein the first mold structure is on a level overlapping a level of the first stack structure, and the alignment structure is on the same level as a level of the first channel structure.

16 . The semiconductor device of claim 14 , wherein the number of the lower horizontal sacrificial layers is less than the number of the lower gate electrodes.

17 . The semiconductor device of claim 14 , wherein a lowermost surface of a lowermost upper horizontal sacrificial layer among the upper horizontal sacrificial layers is on a level lower than a level of an upper surface of the uppermost lower gate electrode.

18 . The semiconductor device of claim 14 , wherein a plurality of upper horizontal sacrificial layers among the upper horizontal sacrificial layers are on a level lower than a level of the upper end of the alignment structure.

19 . A data storage system, comprising:
a semiconductor storage device including a substrate having first and second regions, circuit devices on one side of the substrate, and input/output pads electrically connected to the circuit devices; and a controller electrically connected to the semiconductor storage device through the input/output pads and controlling the semiconductor storage device, wherein the semiconductor storage device further includes:
a first stack structure including lower gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate in the first region;
a first channel structure penetrating the first stack structure and in contact with the substrate;
a second stack structure on the first stack structure and the first channel structure and including upper gate electrodes stacked and spaced apart from each other in the first direction;
a second channel structure penetrating through the second stack structure and connected to the first channel structure;
a first mold structure including lower horizontal sacrificial layers stacked and spaced apart from each other in t

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jinhyuk
• Sung Jeongyong
• Shin Joongshik
• Han Jeehoon

Classifications

• H10W46/301

  for alignment · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/35 Primary

  with a cell select transistor, e.g. NAND · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title