Integrated circuit structures having airgaps for backside signal routing or power delivery

Patent metadata

Field	Value
Publication number	US-12588485-B2
Application number	US-202217855017-A
Country	US
Kind code	B2
Filing date	Jun 30, 2022
Priority date	Jun 30, 2022
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

Structures having airgaps for backside signal routing or power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a first conductive line laterally spaced apart from a second conductive line by an air gap.

First claim

What is claimed is:

1 . An integrated circuit structure, comprising:
a front-side structure comprising:
a device layer having a plurality of nanowire-based transistors; and
a plurality of metallization layers above the nanowire-based transistors of the device layer; and
a backside structure below the nanowire-based transistors of the device layer, the backside structure including a first conductive line laterally spaced apart from a second conductive line by an air gap.

2 . The integrated circuit structure of claim 1 , wherein one or both of the first conductive line or the second conductive line of the backside structure is for signal routing.

3 . The integrated circuit structure of claim 1 , wherein one or both of the first conductive line or the second conductive line of the backside structure is for power delivery.

4 . The integrated circuit structure of claim 1 , wherein the backside structure further includes a third conductive line laterally spaced apart from a fourth conductive line by a second air gap, the second airgap vertically beneath the airgap.

5 . The integrated circuit structure of claim 4 , wherein the backside structure further includes a fifth conductive line laterally spaced apart from a sixth conductive line by a third air gap, the third airgap vertically beneath the second airgap.

6 . An integrated circuit structure, comprising:
a front-side structure comprising:
a device layer having a plurality of fin-based transistors; and
a plurality of metallization layers above the fin-based transistors of the device layer; and
a backside structure below the fin-based transistors of the device layer, the backside structure including a first conductive line laterally spaced apart from a second conductive line by an air gap.

7 . The integrated circuit structure of claim 6 , wherein one or both of the first conductive line or the second conductive line of the backside structure is for signal routing.

8 . The integrated circuit structure of claim 6 , wherein one or both of the first conductive line or the second conductive line of the backside structure is for power delivery.

9 . The integrated circuit structure of claim 6 , wherein the backside structure further includes a third conductive line laterally spaced apart from a fourth conductive line by a second air gap, the second airgap vertically beneath the airgap.

10 . The integrated circuit structure of claim 9 , wherein the backside structure further includes a fifth conductive line laterally spaced apart from a sixth conductive line by a third air gap, the third airgap vertically beneath the second airgap.

11 . A computing device, comprising:
a board; and a component coupled to the board, the component including an integrated circuit structure, comprising:
a front-side structure comprising:
a device layer having a plurality of nanowire-based transistors; and
a plurality of metallization layers above the nanowire-based transistors of the device layer; and
a backside structure below the nanowire-based transistors of the device layer, the backside structure including a first conductive line laterally spaced apart from a second conductive line by an air gap.

12 . The computing device of claim 11 , further comprising:
a memory coupled to the board.

13 . The computing device of claim 11 , further comprising:
a communication chip coupled to the board.

14 . The computing device of claim 11 , wherein the component is a packaged integrated circuit die.

15 . The computing device of claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

16 . A computing device, comprising:
a board; and a component coupled to the board, the component including an integrated circuit structure, comprising:
a front-side structure comprising:
a device layer having a plurality of fin-based transistors; and
a plurality of metallization layers above the fin-based transistors of the device layer; and

a backside structure below the fin-based transistors of the device layer, the backside structure including a first conductive line laterally spaced apart from a second conductive line by an air gap.

17 . The computing device of claim 16 , further comprising:
a memory coupled to the board.

18 . The computing device of claim 16 , further comprising:
a communication chip coupled to the board.

19 . The computing device of claim 16 , wherein the component is a packaged integrated circuit die.

20 . The computing device of claim 16 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

Assignees

• Intel Corp

Inventors

• Sharma Abhishek Anil
• Suthram Sagar
• Ranade Pushkar
• Murthy Anand S
• Ghani Tahir
• Mehandru Rishabh
• Weber Cory

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title