Display panel and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-12588371-B2
Application number	US-202418608893-A
Country	US
Kind code	B2
Filing date	Mar 18, 2024
Priority date	Jul 31, 2018
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

A display panel according to an embodiment of the present invention includes an interlayer insulating layer, a pixel layer including a lower insulating layer between the interlayer insulating layer and a base substrate, an encapsulation layer including a first inorganic layer, and a first blocking groove in the display area, adjacent to a module hole, passing through the interlayer insulating layer to expose a portion of a top surface of the lower insulating layer, and the first blocking groove is surrounded by the first inorganic layer to contact the first inorganic layer.

First claim

What is claimed is:

1 . A display panel comprising:
a base substrate that is divided into a display area and a peripheral area adjacent to the display area; a thin element layer comprising:
a thin film transistor disposed on the base substrate;
an interlayer insulating layer covering the thin film transistor; and
a lower insulating layer disposed between the interlayer insulating layer and the base substrate;
an organic light emitting element disposed on the display area and connected to the thin film transistor; an encapsulation layer disposed on the thin element layer and comprising a first inorganic layer, a second inorganic layer disposed on the first inorganic layer, and an organic layer disposed between the first inorganic layer and the second inorganic layer; a module hole defined in the display area and penetrating from a rear surface of the base substrate to a top surface of the encapsulation layer; and a first blocking groove defined in the display area adjacent to the module hole and penetrating through the interlayer insulating layer, wherein a portion of the first inorganic layer that overlaps the first blocking groove is disposed inside the first blocking groove and covers a side of the first blocking groove.

2 . The display panel of claim 1 , wherein the thin film transistor comprises a semiconductor pattern disposed on the base substrate, a control electrode spaced apart from the semiconductor pattern and overlapping the semiconductor pattern, and input and output electrodes which are spaced apart from each other and each of which is connected to the semiconductor pattern,
wherein the lower insulating layer comprises a first insulating layer disposed between the control electrode and the semiconductor pattern and a second insulating layer disposed between the first insulating layer and the interlayer insulating layer, and wherein the first blocking groove exposes a portion of a top surface on the second insulating layer.

3 . The display panel of claim 1 , wherein the first blocking groove has an under-cut shape, and
an inner surface of the first blocking groove is covered by the first inorganic layer.

4 . The display panel of claim 1 , further comprising an inorganic material pattern including an opening defining the first blocking groove together with the penetrated portion of the interlayer insulating layer and disposed on the interlayer insulating layer,
wherein the inorganic material pattern contacts the first inorganic layer.

5 . The display panel of claim 1 , wherein the first blocking groove has a closed shape surrounding the module hole in a plan view.

6 . The display panel of claim 1 , further comprising a second blocking groove spaced apart from the first blocking groove so as to be defined between the first blocking groove and the organic light emitting element in a plan view, the second blocking groove penetrating through the interlayer insulating layer,
wherein an inner surface of the second blocking groove is covered by the first inorganic layer, and the organic layer covers the first inorganic layer.

7 . The display panel of claim 1 , further comprising a third blocking groove spaced apart from the first blocking groove so as to be defined between the module hole and the first blocking groove in a plan view, the third blocking groove penetrating through the interlayer insulating layer,
wherein an inner surface of the third blocking groove is covered by the first inorganic layer, and the second inorganic layer covers the first inorganic layer.

8 . The display panel of claim 1 , further comprising a filling member which is disposed inside the first blocking groove surrounded by the first inorganic layer and comprises an organic material.

9 . The display panel of claim 8 , wherein the second inorganic layer covers the filling member and the first inorganic layer.

10 . The display panel of claim 1 , wherein the base substrate comprises at least one of glass, plastic, or a metal.

11 . An electronic apparatus comprising:
a base substrate that is divided into a display area and a peripheral area adjacent to the display area in a plan view; an organic light emitting element disposed on the display area and comprising a first electrode, a second electrode disposed on the first electrode, and an emission layer disposed between the first electrode and the second electrode; a thin element layer comprising:
a thin film transistor connected to the organic light emitting element;
an interlayer insulating layer on which the first electrode is disposed and which is disposed between the thin film transistor and the organic light emitting element;
a lower insulating layer disposed between the base substrate and the interlayer insulating layer; and
an inorganic material pattern disposed on the interlayer insulating layer;
an encapsulation layer disposed on the thin element layer and comprising:
a first inorganic layer;
a second inorganic layer disposed on the first inorganic layer; and
an organic layer disposed between the first inorganic layer and the second inorganic layer;
a module hole defined in the display area and penetrating from a rear surface of the base substrate to a top surface of the encapsulation layer; a blocking groove disposed in the display area and defined by a pattern part adjacent to the module hole and an opening defined in the inorganic material pattern overlapping the pattern part; and an electronic module configured to overlap the module hole, wherein the pattern part passes through the interlayer insulating layer, wherein a portion of the first inorganic layer that overlaps the blocking groove is disposed inside the blocking groove and covers a side of the blocking groove.

12 . The electronic apparatus of claim 11 , wherein the inorganic material pattern contacts the first inorganic layer.

13 . The electronic apparatus of claim 11 , wherein the opening has a width less than a width of the pattern part in a cross-section.

14 . The electronic apparatus of claim 11 , wherein the inorganic material pattern is disposed on the interlayer insulating layer so as to cover at least a portion of the pattern part, and
in a cross-section, a width of the opening is smaller than a width of the pattern part.

15 . The electronic apparatus of claim 11 , wherein an inner surface of the module hole is defined as:
an end of the penetrated base substrate; and an end of each of the lower insulating layer, the first inorganic layer, and the second inorganic layer, which are aligned with the end of the base substrate.

16 . The electronic apparatus of claim 11 , wherein the inorganic material pattern and a portion of the top surface of the lower insulating layer contact the first inorganic layer.

17 . The electronic apparatus of claim 11 , wherein the blocking groove has a closed shape surrounding the module hole in the plan view.

18 . The electronic apparatus of claim 11 , wherein the electronic module comprises at least one of an audio output module, a light emitting module, a light receiving module, or a camera module.

19 . A method for manufacturing a display panel, the method comprising:
forming a thin element layer comprising a pixel comprising a plurality of insulating layers on a display area of a base substrate that is divided into the display area comprising a hole area and a peripheral area adjacent to the display area; removing a portion of one of the insulating layers overlapping the hole area to form a blocking groo

Assignees

• Samsung Display Co Ltd

Inventors

• Seo Junghan
• Sung Woo Yong

Classifications

• H10K59/8731 Primary

  multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers · CPC title

• H10K59/1201

  Manufacture or treatment · CPC title

• H10K77/10

  Substrates, e.g. flexible substrates · CPC title

• H10K71/00

  Manufacture or treatment specially adapted for the organic devices covered by this subclass · CPC title

• H10K59/65

  OLEDs integrated with inorganic image sensors · CPC title