Method of manufacturing display device with block members having different heights

Patent metadata

Field	Value
Publication number	US-9966566-B2
Application number	US-201715476661-A
Country	US
Kind code	B2
Filing date	Mar 31, 2017
Priority date	Nov 17, 2015
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

A display device and a method of manufacturing the display device are disclosed. In one aspect, the display device includes a substrate including a display region and a peripheral region. A first block member is in the peripheral region and surrounding display structures, the first block member having a first height. A second block member is spaced apart from the first block member in a first direction extending from the display region to the peripheral region, the second block member surrounding the first block member, the second block member having a second height that is greater than the first height. A first encapsulation layer is over the display structures, the first block member, and the second block member. A second encapsulation layer is over the first encapsulation layer, the second encapsulation layer overlapping at least a portion of the first block member in the depth dimension of the display device.

First claim

What is claimed is:

1. A method of manufacturing display device, comprising:
providing a substrate including a display region and a peripheral region surrounding the display region;
forming a plurality of display structures in the display region;
forming a first block member in the peripheral region and surrounding the display structures, the first block member having a first height;
forming a second block member spaced apart from the first block member in a first direction extending from the display region to the peripheral region, the second block member surrounding the first block member and having a second height that is greater than the first height;
forming a first encapsulation layer over the display structures, the first block member, and the second block member, wherein the first encapsulation layer is formed of an inorganic material;
forming a second encapsulation layer over the first encapsulation layer, the second encapsulation layer overlapping at least a portion of the first block member in the depth dimension of the display device, wherein the second encapsulation layer is formed of an organic material; and
forming a third encapsulation layer over the first and second encapsulation layers, the third encapsulation layer formed of the inorganic material.

2. The method of claim 1 , wherein forming the first and second block members includes:
forming a preliminary planarization layer over the substrate;
partially removing the preliminary planarization layer so as to form a planarization layer in the display region and a lower block pattern in the peripheral region;
forming a preliminary pixel defining layer over the lower block pattern and the planarization layer; and
partially removing the preliminary pixel defining layer so as to form a pixel defining layer in the display region and a first block member and an upper block pattern in the peripheral region, the upper block pattern surrounding the first block member and located on the lower block pattern.

3. The method of claim 2 , wherein the preliminary pixel defining layer is partially removed using a half tone slit mask, wherein the half tone slit mask includes an opening region, a light shielding region, a slit region, and a transflective region, wherein the preliminary pixel defining layer is completely removed in the opening region and is not removed in the light shielding region, and wherein the preliminary pixel defining layer is partially removed in the transflective and slit regions.

4. The method of claim 3 , wherein the pixel defining layer is formed in the transflective region of the half tone slit mask, wherein the first block member is formed in the slit region of the half tone slit mask, and wherein the lower block pattern and the upper block pattern are formed in the light shielding region of the half tone slit mask.

5. The method of claim 4 , wherein the lower and upper block patterns form the second block member.

6. The method of claim 5 , wherein an upper surface of the first block member is uneven.

7. The method of claim 5 , wherein an upper surface of the first block member has a concave portion and a convex portion.

8. The method of claim 5 , wherein an upper surface of the first block member has a plurality of recesses.

9. The method of claim 1 , further comprising forming semiconductor elements on the substrate before forming the display structures.

10. The method of claim 9 , wherein forming the semiconductor elements includes:
forming active layers over the substrate;
forming a gate insulation layer over the active layers;
forming gate electrodes over the gate insulation layer;
forming an insulating interlayer over the gate electrode and the gate insulation layer; and
forming source and drain electrodes and first and second power supply voltage lines over the insulating interlayer.

11. The method of claim 10 , wherein forming the display structures includes:
forming a planarization layer over the source and drain electrodes and the first and second power supply voltage lines;
forming lower electrodes over the planarization layer;
forming a pixel defining layer that exposes a portion of each of the lower electrodes;
forming light emitting layers over the lower electrodes; and
forming an upper electrode over the light emitting layers and the pixel defining layer.

12. The method of claim 1 , wherein a ratio of the first height to the second height is in the range of about 0.6:1 to about 0.8:1, wherein the first height is defined from an upper surface of the substrate to an upper surface of the first block member, and wherein the second height is defined from the upper surface of the substrate to an upper surface of the second block member.

13. The method of claim 1 , wherein forming the first and second block members includes:
forming a preliminary pixel defining layer; and
partially removing the preliminary pixel defining layer so as to form a pixel defining layer and first and second block members, the second block member surrounding the first block member.

14. The method of claim 13 , wherein the preliminary pixel defining layer is partially removed using a half tone slit mask, wherein the half tone slit mask includes an opening region, a light shielding region, a slit region, and a transflective region, wherein the preliminary pixel defining layer is completely removed in the opening region and is not removed in the light shielding region, and wherein the preliminary pixel defining layer is partially removed in the transflective and slit regions.

15. The method of claim 14 , wherein the pixel defining layer is formed in the transflective region of the half tone slit mask, wherein the first block member is formed in the slit region of the half tone slit mask, and wherein the second block member is formed in the light shielding region of the half tone slit mask.

Assignees

• Samsung Display Co Ltd

Inventors

• Shin Sung-Young

Classifications

• G02F1/13394

  spacers regularly patterned on the cell subtrate, e.g. walls, pillars (G02F1/133377 takes precedence) · CPC title

• G02F1/133345

  Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence) · CPC title

• G02F2201/50

  Protective arrangements · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• H10K50/844

  Encapsulations · CPC title