Display panel and mobile terminal

Patent metadata

Field	Value
Publication number	US-12588285-B2
Application number	US-202217910800-A
Country	US
Kind code	B2
Filing date	Aug 30, 2022
Priority date	Jul 8, 2022
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

The present disclosure provides a display panel and a mobile terminal, the display panel includes a substrate and a thin film transistor layer, the thin film transistor layer including a semiconductor layer, an insulating layer and a first metal layer, the insulating layer being disposed on the substrate and the semiconductor layer and covering the semiconductor layer, the first metal layer being disposed on the insulating layer, the insulating layer including at least one via hole, the first metal layer being connected to the semiconductor layer through the via hole, and an included angle between a sidewall of the via hole and a bottom surface of the insulating layer being greater than or equal to 85 degrees and less than or equal to 90 degrees.

First claim

What is claimed is:

1 . A display panel, comprising:
a substrate; a thin film transistor layer disposed on the substrate, wherein the thin film transistor layer comprises a semiconductor layer, an insulating layer, and a first metal layer stacked on the substrate, the insulating layer is disposed on the substrate and the semiconductor layer and covers the semiconductor layer, and the first metal layer is disposed on the insulating layer; a spacing layer disposed on a side of the insulating layer away from the substrate, wherein the spacing layer comprises at least one open slot penetrating through the spacing layer; a flat layer, a passivation layer, and a first electrode layer stacked on the spacing layer, wherein a first connection via hole penetrating through the flat layer and the passivation layer is provided in the display panel, the at least one open slot comprises a first open slot in communication with the first connection via hole, the first connection via hole is in communication with the first open slot, the first metal layer comprises a first signal line disposed in the first open slot, the first electrode layer comprises a bridge section, one end of the bridge section is connected with the first signal line through the first connection via hole; and wherein the insulating layer comprises at least one via hole, the first metal layer is connected to the semiconductor layer through the via hole, an included angle between a sidewall of the via hole and a bottom surface of the insulating layer is greater than or equal to 85 degrees and less than or equal to 90 degrees, and an included angle between a sidewall of the first connection via hole and the bottom surface of the flat layer is greater than or equal to 85 degrees and less than or equal to 90 degrees.

2 . The display panel according to claim 1 , wherein the via hole comprises a first opening on a side away from the substrate and a second opening on a side close to the substrate;
wherein a ratio of a width of the first opening to a width of the second opening is greater than or equal to 0.9 and less than or equal to 1.1.

3 . The display panel according to claim 1 , wherein the substrate comprises a base and a buffer layer disposed on the base, and a thickness of the insulating layer is greater than twice a thickness of the buffer layer.

4 . The display panel according to claim 3 , wherein the display panel further comprises a conductive filling portion disposed in the via hole, and the first metal layer is connected to the semiconductor layer through the conductive filling portion.

5 . The display panel according to claim 4 , wherein a resistivity of the conductive filling portion is less than 5.48×10 −6 Ω·m.

6 . The display panel according to claim 4 , wherein an orthographic projection of the first metal layer on the base covers an orthographic projection of the conductive filling portion on the base.

7 . The display panel according to claim 1 , wherein the open slot is provided in communication with the via hole; and
wherein the first metal layer is disposed in the open slot, and an included angle between a sidewall of the open slot and a bottom surface of the spacing layer is greater than or equal to 85 degrees and less than or equal to 90 degrees.

8 . The display panel according to claim 7 , wherein a ratio of a depth of the open slot to a width of the open slot is greater than or equal to 0.2 and less than or equal to 1.

9 . The display panel according to claim 7 , wherein the display panel further comprises a second metal layer;
the thin film transistor layer comprises a plurality of thin film transistors, the first metal layer comprises a source and a drain of the thin film transistor, the semiconductor layer comprises an active layer of the thin film transistor, and the second metal layer comprises a gate of the thin film transistor; the insulating layer comprises a plurality of via holes, the plurality of via holes comprise a first via hole and a second via hole located above the active layer, the drain is connected to the active layer through the first via hole, and the source is connected to the active layer through the second via hole.

10 . The display panel according to claim 9 , wherein the display panel further comprises a conductive filling portion, the conductive filling portion comprises a first filling portion disposed in the first via hole and a second filling portion disposed in the second via hole, the drain is connected to the active layer through the first filling portion, and the source is connected to the active layer through the second filling portion.

11 . The display panel according to claim 9 , wherein the spacing layer comprises a plurality of open slots, the plurality of open slots comprises a third open slot in communication with the first via hole and a second open slot in communication with the second via hole; and
wherein the drain is disposed in the third open slot and the source is disposed in the second open slot.

12 . The display panel according to claim 11 , wherein the semiconductor layer is located between the gate and the substrate, the insulating layer comprises a gate insulating layer disposed between the semiconductor layer and the gate, and an interlayer insulating layer disposed on a side of the gate insulating layer away from the gate;
both the first via hole and the second via hole pass through the interlayer insulating layer and the gate insulating layer; and wherein the substrate comprises a base and a buffer layer disposed on the base, and a thickness of the interlayer insulating layer is greater than twice a thickness of the buffer layer.

13 . The display panel according to claim 11 , wherein the gate is located between the semiconductor layer and the substrate, the insulating layer comprises an interlayer insulating layer disposed between the semiconductor layer and the first metal layer, and a gate insulating layer is disposed on a side of the semiconductor layer away from the interlayer insulating layer;
both the first via hole and the second via hole pass through the interlayer insulating layer; and wherein the substrate comprises a base and a buffer layer disposed on the base, and a thickness of the interlayer insulating layer is greater than twice a thickness of the buffer layer.

14 . The display panel according to claim 11 , wherein the display panel further comprises a second electrode layer stacked on the spacing layer;
a second connection via hole penetrating through the flat layer and the passivation layer is provided in the display panel, and the second connection via hole is communicated with the third open slot; the first electrode layer comprises a first electrode connected to the drain through the second connection via hole; and wherein an included angle between a sidewall of the second connection via hole and a bottom surface of the flat layer is greater than or equal to 85 degrees and less than or equal to 90 degrees.

15 . The display panel according to claim 14 , wherein a third connection via hole penetrating through the passivation layer is provided in the display panel;
the plurality of open slots comprise a first open slot in communication with the first connection via hole, the first connection via hole is in communication with the first open slot, the first metal layer comprises a first signal line disposed in the first open slot, the second electrode layer comprises a touch electrode, the first electrode layer comprises a bridge section, one end of the bridge section is connected with the first signal line through the first conne

Assignees

• Wuhan China Star Optoelectronics Technology Co Ltd

Inventors

• Ai Fei
• Luo Chengzhi

Classifications

• G02F1/13338

  Input devices, e.g. touch panels · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/40 Primary

  characterised by multiple TFTs · CPC title

• H10D86/451 Primary

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title