Array substrate used in liquid crystal panel and manufacturing method for the same

Patent metadata

Field	Value
Publication number	US-9759941-B2
Application number	US-201514901250-A
Country	US
Kind code	B2
Filing date	Nov 27, 2015
Priority date	Nov 24, 2015
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

An array substrate is provided. The array substrate includes: a substrate; a LTPS TFT disposed above the substrate; a planarization layer covering the LTPS TFT; a via hole formed in the planarization layer, wherein the via hole reveals a drain electrode of the LTPS TFT; multiple common electrodes and receiving electrodes disposed separately on the planarization layer, wherein the multiple common electrode function as a driving electrode in a touch stage, and the multiple common electrodes which are disposed separately are connected with each other; a passivation layer which covers the multiple common electrodes and the multiple receiving electrodes and the planarization layer; and a pixel electrode disposed on the passivation layer, wherein, the pixel electrode is contacted with the drain electrode through the via hole. A manufacturing method for the array substrate is also provided. The present invention can reduce one manufacturing process and decrease production cost.

First claim

What is claimed is:

1. An array substrate used in a liquid crystal panel, comprising:
a substrate;
a low-temperature poly-silicon thin-film transistor (LTPS TFT) disposed above the substrate;
a planarization layer which covers the LTPS TFT;
a via hole formed in the planarization layer, wherein, the via hole reveals a drain electrode of the LTPS TFT;
multiple common electrodes and multiple receiving electrodes which are disposed separately on the planarization layer, wherein, the multiple common electrode function as a driving electrode in a touch stage, and the multiple common electrodes which are disposed separately are connected with each other;
a passivation layer which covers the multiple common electrodes and the multiple receiving electrodes and the planarization layer; and
a pixel electrode disposed on the passivation layer, wherein, the pixel electrode is contacted with the drain electrode through the via hole.

2. The array substrate according to claim 1 , wherein, the array substrate further includes:
a third through hole in the passivation layer, wherein the third through hole reveals the common electrode; and
a connection electrode which is not contacted with the pixel electrode on the passivation layer;
wherein, the connection electrode is contacted with the common electrodes through the third through hole such that the multiple common electrodes which are disposed separately are connected with each other.

3. The array substrate according to claim 1 , wherein, the multiple common electrodes and the multiple receiving electrodes are formed simultaneously.

4. The array substrate according to claim 2 , wherein, the multiple common electrodes and the multiple receiving electrodes are formed simultaneously.

5. The array substrate according to claim 2 , wherein, the pixel electrode and the connection electrode are formed simultaneously.

6. The array substrate according to claim 1 , wherein, the array substrate further includes:
a light-shielding layer disposed between the substrate and the LTPS TFT, wherein, the light-shielding layer is disposed oppositely to the LTPS TFT; and
a first insulation layer disposed between the light-shielding layer and the LTPS TFT, wherein, the first insulation layer covers the light-shielding layer and the substrate.

7. The array substrate according to claim 5 , wherein, the LTPS TFT includes:
a polysilicon layer disposed on the first insulation layer;
a second insulation layer which covers the polysilicon layer on the first insulation layer;
a gate electrode disposed on the second insulation layer;
a third insulation layer which covers the gate electrode on the second insulation layer;
a first through hole and a second through hole in the second insulation layer and the third insulation layer, wherein, the first through hole and the second through hole reveal a surface of the polysilicon layer; and
a source electrode and the drain electrode disposed on the third insulation layer, wherein, the source electrode fills the first through hole and contacts the surface of the polysilicon layer, and the drain electrode fills the second through hole and contacts the surface of the polysilicon layer;
wherein, the planarization layer is disposed on the third insulation layer and covers the source electrode and the drain electrode.

8. A manufacturing method for an array substrate of a liquid crystal panel, comprising:
providing a substrate;
forming a low-temperature poly-silicon thin-film transistor (LTPS TFT) above the substrate;
forming a planarization layer which covers the LTPS TFT;
forming a via hole in the planarization layer, wherein, the via hole reveals a drain electrode of the LTPS TFT;
simultaneously forming multiple common electrodes and multiple receiving electrodes which are disposed separately on the planarization layer, wherein, the multiple common electrodes function as a driving electrode in a touch stage, and the multiple common electrodes which are disposed separately are connected with each other;
forming a passivation layer which covers the multiple common electrodes and the multiple receiving electrodes and the planarization layer; and
forming a pixel electrode on the passivation layer, wherein, the pixel electrode is contacted with the drain electrode through the via hole.

9. The manufacturing method according to claim 8 , wherein, the manufacturing method further includes:
after forming the passivation layer, forming a third through hole in the passivation layer, wherein the third through hole reveals the common electrode; and
when forming the pixel electrode, simultaneously forming a connection electrode which is not contacted with the pixel electrode on the passivation layer;
wherein, the connection electrode is contacted with the common electrodes through the third through hole such that the multiple common electrodes which are disposed separately are connected with each other.

10. The manufacturing method according to claim 8 , wherein, the manufacturing method further includes:
before forming the LTPS TFT, forming a light-shielding layer on the substrate, wherein, the light-shielding layer is disposed oppositely to the LTPS TFT; and
forming a first insulation layer which covers the light-shielding layer on the substrate.

11. The manufacturing method according to claim 9 , wherein, the manufacturing method further includes:
before forming the LTPS TFT, forming a light-shielding layer on the substrate, wherein, the light-shielding layer is disposed oppositely to the LTPS TFT; and
forming a first insulation layer which covers the light-shielding layer on the substrate.

12. The manufacturing method according to claim 8 , wherein, the step of forming a LTPS TFT includes:
forming a polysilicon layer on the first insulation layer;
forming a second insulation layer which covers the polysilicon layer on the first insulation layer;
forming a gate electrode on the second insulation layer;
forming a third insulation layer which covers the gate electrode on the second insulation layer;
forming a first through hole and a second through hole in the second insulation layer and the third insulation layer, wherein, the first through hole and the second through hole reveal a surface of the polysilicon layer; and
forming a source electrode and the drain electrode on the third insulation layer, wherein, the source electrode fills the first through hole and contacts the surface of the polysilicon layer, and the drain electrode fills the second through hole and contacts the surface of the polysilicon layer;
wherein, the planarization layer is disposed on the third insulation layer and covers the source electrode and the drain electrode.

13. The manufacturing method according to claim 9 , wherein, the step of forming a LTPS TFT includes:
forming a polysilicon layer on the first insulation layer;
forming a second insulation layer which covers the polysilicon layer on the first insulation layer;
forming a gate electrode on the second insulation layer;
forming a third insulation layer which covers the gate electrode on the second insulation layer;
forming a first through hole and a second through hole in the second insulation layer and the third insulation layer, wherein, the first through hole and the second through hole reveal a surface of the polysilicon layer; and
forming a source electrode and the drain electrode on the third insulation layer, wherein, the source electrode fills the first through hole and contacts the surface of the polysilicon layer, and the drain electrode fills the second through hole and contacts the surface of the polysilicon layer;

Assignees

• Shenzhen China Star Optoelect
• Wuhan China Star Optoelectronics Technology Co Ltd

Inventors

• Yang Zuyou

Classifications

• G02F1/136227

  Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title

• G06F2203/04103

  Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices · CPC title

• G02F1/133345

  Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence) · CPC title

• G02F2202/104

  poly-Si · CPC title

• G02F1/136209

  Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element · CPC title