Thin-film transistor and manufacturing method thereof, and display substrate

Patent metadata

Field	Value
Publication number	US-12588284-B2
Application number	US-202117910133-A
Country	US
Kind code	B2
Filing date	Dec 27, 2021
Priority date	Dec 27, 2021
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

Provided are a thin-film transistor and a manufacturing method thereof, and a display substrate, belonging to the technical field of thin-film transistors. The thin-film transistor includes: a base substrate; a gate electrode on the base substrate; an active layer on a side of the gate electrode away from the base substrate, an orthographic projection of the active layer onto the base substrate overlapping with an orthographic projection of the gate electrode onto the base substrate; and a first electrode and a second electrode on a side of the active layer away from the base substrate, the first electrode being one of a source electrode and a drain electrode, and the second electrode being the other of the source electrode and the drain electrode. Specifically the active layer includes a channel region corresponding to a gap between the first electrode and the second electrode, and a width direction of the channel region is perpendicular or substantially perpendicular to an extending direction of the gate electrode. According to the embodiments of the present disclosure, the illumination stability of the thin-film transistor can be improved without reducing the transmittance of the substrate.

First claim

What is claimed is:

1 . A thin-film transistor, comprising:
a base substrate; a gate electrode on the base substrate; an active layer on a side of the gate electrode away from the base substrate, an orthographic projection of the active layer onto the base substrate overlapping with an orthographic projection of the gate electrode onto the base substrate; and a first electrode and a second electrode on a side of the active layer away from the base substrate, the first electrode being one of a source electrode and a drain electrode, and the second electrode being the other of the source electrode and the drain electrode, wherein the active layer comprises a channel region corresponding to a gap between the first electrode and the second electrode, and a width direction of the channel region is perpendicular or substantially perpendicular to an extending direction of the gate electrode; and wherein the extending direction of the gate electrode is perpendicular or substantially perpendicular to an extending direction of a gate line in a display substrate comprising the thin-film transistor; the gate electrode is connected to the gate line; wherein the active layer comprises a first boundary and a second boundary that are parallel or substantially parallel to the extending direction of the gate electrode, the gate electrode comprises a third boundary and a fourth boundary that are parallel or substantially parallel to the extending direction of the gate electrode; and the shortest distance between the first boundary and the third boundary is b, and b is greater than 5 μm; wherein orthographic projections of the first electrode and the second electrode onto the base substrate do not overlap with the orthographic projection of the gate electrode onto the base substrate; wherein in a region where the orthographic projection of the active layer onto the base substrate overlaps with the orthographic projection of the gate electrode onto the base substrate, a width of the gate electrode is greater than a width of the gate line along the extending direction of the gate electrode.

2 . The thin-film transistor according to claim 1 , wherein a distance between the first boundary and the third boundary is smaller than a distance between the first boundary and the fourth boundary.

3 . The thin-film transistor according to claim 1 , wherein the gate electrode comprises a fifth boundary and a sixth boundary perpendicular to or substantially perpendicular to the extending direction of the gate electrode, the shortest distance between the fifth boundary and the sixth boundary is d, the channel region comprises a seventh boundary and an eighth boundary perpendicular to or substantially perpendicular to the extending direction of the gate electrode, and the shortest distance between the seventh boundary and the eighth boundary is L, wherein a difference between d and L is less than or equal to 4 μm.

4 . The thin-film transistor according to claim 1 , wherein the shortest distance between a first orthographic projection of the first electrode onto the base substrate and a second orthographic projection of the gate electrode onto the base substrate is a, and the shortest distance between a third orthographic projection of the second electrode onto the base substrate and the second orthographic projection of the gate electrode onto the base substrate is also a.

5 . The thin-film transistor according to claim 1 , wherein the width of the first electrode in a direction perpendicular to the extending direction of the gate electrode is the same as the width of the second electrode in the direction perpendicular to the extending direction of the gate electrode, both being c.

6 . The thin-film transistor according to claim 5 , wherein c is greater than W, a difference between c and W is 2-3 μm, and W is the width of the channel region of the thin-film transistor.

7 . A display substrate, comprising a thin-film transistor, a gate electrode of the thin-film transistor being connected to a gate line of the display substrate, and an extending direction of the gate electrode being perpendicular or substantially perpendicular to an extending direction of the gate line,
the thin-film transistor comprising: a base substrate; the gate electrode on the base substrate; an active layer on a side of the gate electrode away from the base substrate, an orthographic projection of the active layer onto the base substrate overlapping with an orthographic projection of the gate electrode onto the base substrate; and a first electrode and a second electrode on a side of the active layer away from the base substrate, the first electrode being one of a source electrode and a drain electrode, and the second electrode being the other of the source electrode and the drain electrode, wherein the active layer comprises a channel region corresponding to a gap between the first electrode and the second electrode, and a width direction of the channel region is perpendicular or substantially perpendicular to the extending direction of the gate electrode; wherein the active layer comprises a first boundary and a second boundary that are parallel or substantially parallel to the extending direction of the gate electrode, the gate electrode comprises a third boundary and a fourth boundary that are parallel or substantially parallel to the extending direction of the gate electrode; and the shortest distance between the first boundary and the third boundary is b, and b is greater than 5 μm; wherein orthographic projections of the first electrode and the second electrode onto the base substrate do not overlap with the orthographic projection of the gate electrode onto the base substrate; wherein in a region where the orthographic projection of the active layer onto the base substrate overlaps with the orthographic projection of the gate electrode onto the base substrate, a width of the gate electrode is greater than a width of the gate line along the extending direction of the gate electrode.

8 . The display substrate according to claim 7 , wherein a data line of the display substrate is connected to the first electrode or the second electrode via a lead, and the lead is parallel or substantially parallel to the gate line.

9 . The display substrate according to claim 7 , wherein a distance between the first boundary and the third boundary is smaller than a distance between the first boundary and the fourth boundary.

10 . The display substrate according to claim 7 , wherein the gate electrode comprises a fifth boundary and a sixth boundary perpendicular to or substantially perpendicular to the extending direction of the gate electrode, the shortest distance between the fifth boundary and the sixth boundary is d, the channel region comprises a seventh boundary and an eighth boundary perpendicular to or substantially perpendicular to the extending direction of the gate electrode, and the shortest distance between the seventh boundary and the eighth boundary is L, wherein a difference between d and L is less than or equal to 4 μm.

11 . The display substrate according to claim 7 , wherein the shortest distance between a first orthographic projection of the first electrode onto the base substrate and a second orthographic projection of the gate electrode onto the base substrate is a, and the shortest distance between a third orthographic projection of the second electrode onto the base substrate and the second orthographic projection of the gate electrode onto the base substrate is also a.

12 . A method for manufacturing a thin-film transistor, comprising:
providing a base substrate; forming a gate electrode on the bas

Assignees

• Boe Technology Group Co Ltd

Inventors

• Hu hehe
• Qu Yan
• He Jiayu
• Zhao Kun
• Huang Jie
• Li Zhengliang
• Ning ce
• Wang Dongfang
• Liu Fengjuan
• Yao Nianqi
• Li Feifei
• Zhang Shunhang
• Im Yunsik
• Lei Liping

Classifications

• H10D64/258

  characterised by the relative positions of the source or drain electrodes with respect to the gate electrode · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/6732

  Bottom-gate only TFTs · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title