Thin Film Transistor and Mnaufacturing Method Thereof, Array Substrate and Display Device

Patent metadata

Field	Value
Publication number	US-2016013209-A1
Application number	US-201414415660-A
Country	US
Kind code	A1
Filing date	Jun 30, 2014
Priority date	Sep 2, 2013
Publication date	Jan 14, 2016
Grant date	—

Abstract

The present invention provides a thin film transistor and a manufacturing method thereof, an array substrate and a display device. The thin film transistor comprises a gate electrode, an active layer, an etch stop layer, a source electrode and a drain electrode, the etch stop layer is provided between the active layer and the source and drain electrodes, a first via hole and a second via hole are formed in the etch stop layer, the source electrode is connected with the active layer through the first via hole, the drain electrode is connected with the active layer through the second via hole, and the gate electrode is overlapped with a part of the first via hole and a part of the second via hole respectively and is overlapped with a portion between the first via hole and the second via hole.

First claim

1 - 15 . (canceled)

16 . A thin film transistor, comprising a gate electrode, an active layer, an etch stop layer, a source electrode and a drain electrode, wherein the etch stop layer is provided between the active layer and the source and drain electrodes, a first via hole and a second via hole are formed in the etch stop layer, the source electrode is connected with the active layer through the first via hole, the drain electrode is connected with the active layer through the second via hole, wherein the gate electrode is overlapped with a part of the first via hole and a part of the second via hole respectively and is overlapped with a portion between the first via hole and the second via hole.

17 . The thin film transistor of claim 16 , wherein the first via hole and the second via hole are of rectangles with rounded corners; a projection of one side of the gate electrode overlapped with the first via hole on a plane of the first via hole is respectively intersected with two opposite straight sides of the first via hole; and a projection of another side of the gate electrode overlapped with the second via hole on a plane of the second via hole is respectively intersected with two opposite straight sides of the second via hole.

18 . The thin film transistor of claim 17 , wherein the gate electrode is overlapped with at least two rounded corner parts at one side of the first via hole and at least two rounded corner parts at one side of the second via hole, respectively.

19 . The thin film transistor of claim 16 , wherein the gate electrode is overlapped with at least half of the first via hole and at least half of the second via hole, respectively.

20 . The thin film transistor of claim 16 , wherein shapes of the first via hole and the second via hole are identical to each other.

21 . The thin film transistor of claim 19 , wherein areas of the first via hole and the second via hole are equal to each other.

22 . The thin film transistor of claim 16 , wherein the active layer is an indium gallium zinc oxide film layer.

23 . The thin film transistor of claim 16 , wherein the etch stop layer is a silicon oxide film layer, a silicon nitride film layer or a composite layer formed by silicon oxide and silicon nitride.

24 . The thin film transistor of claim 16 , wherein the gate electrode, a gate insulating layer, the active layer, the etch stop layer, the source electrode and the drain electrode are sequentially provided from a substrate side for providing the thin film transistor.

25 . The thin film transistor of claim 16 , wherein the active layer, the etch stop layer, the source electrode and the drain electrode, a gate insulating layer and the gate electrode are sequentially provided from a substrate side for providing the thin film transistor.

26 . A display device, comprising an array substrate, the array substrate comprising a thin film transistor, wherein
the thin film transistor comprises a gate electrode, an active layer, an etch stop layer, a source electrode and a drain electrode, the etch stop layer is provided between the active layer and the source and drain electrodes, a first via hole and a second via hole are formed in the etch stop layer, the source electrode is connected with the active layer through the first via hole, and the drain electrode is connected with the active layer through the second via hole, and the gate electrode is overlapped with a part of the first via hole and a part of the second via hole respectively and is overlapped with a portion between the first via hole and the second via hole.

27 . The display device of claim 26 , wherein the first via hole and the second via hole are of rectangles with rounded corners;
a projection of one side of the gate electrode overlapped with the first via hole on a plane of the first via hole is respectively intersected with two opposite straight sides of the first via hole; and a projection of another side of the gate electrode overlapped with the second via hole on a plane of the second via hole is respectively intersected with two opposite straight sides of the second via hole.

28 . The display device of claim 27 , wherein the gate electrode is overlapped with at least two rounded corner parts at one side of the first via hole and at least two rounded corner parts at one side of the second via hole, respectively.

29 . The display device of claim 26 , wherein the gate electrode is overlapped with at least half of the first via hole and at least half of the second via hole, respectively.

30 . The display device of claim 26 , wherein shapes of the first via hole and the second via hole are identical to each other, and areas of the first via hole and the second via hole are equal to each other.

31 . The display device of claim 26 , wherein the active layer is an indium gallium zinc oxide film layer.

32 . The display device of claim 26 , wherein the etch stop layer is a silicon oxide film layer, a silicon nitride film layer or a composite layer formed by silicon oxide and silicon nitride.

33 . A manufacturing method of a thin film transistor, comprising steps of:
forming a gate electrode; forming an active layer; forming an etch stop layer, and forming a first via hole and a second via hole in the etch stop layer by a patterning process, so that the gate electrode is overlapped with a part of the first via hole and a part of the second via hole and is overlapped with a portion between the first via hole and the second via hole; and forming a source and drain metal layer, and forming a source electrode and a drain electrode by a patterning process, so that the source electrode is connected with the active layer through the first via hole, and the drain electrode is connected with the active layer through the second via hole.

34 . The manufacturing method of a thin film transistor of claim 33 , wherein the gate electrode is overlapped with at least half of the first via hole and at least half of the second via hole, respectively.

35 . The manufacturing method of a thin film transistor of claim 33 , wherein the first via hole and the second via hole are of rectangles with rounded corners, and the gate electrode is overlapped with at least two rounded corner parts at one side of the first via hole and at least two rounded corner parts at one side of the second via hole, respectively.

Assignees

• Boe Technology Group Co Ltd
• Hefei Boe Optoelectronics Tech

Inventors

• Yang Haipeng
• Yoon Yongjun
• Tu Zhizhong
• Kim Jaikwang

Classifications

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title