Semiconductor structure and related methods

Patent metadata

Field	Value
Publication number	US-12588283-B2
Application number	US-202117446269-A
Country	US
Kind code	B2
Filing date	Aug 27, 2021
Priority date	Aug 27, 2021
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

Methods and associated devices including the fabrication of a semiconductor structure that provides a silicon-on-insulator substrate. The semiconductor structure may be formed by providing a base substrate, forming a sacrificial layer over the base structure, and forming a semiconductor layer over the sacrificial layer. The sacrificial layer is removed to form a void that is filled with oxide. The semiconductor structure includes a dielectric support feature extending through the semiconductor and oxide layers and/or a portion of the oxide layer extends to the surface of the semiconductor layer.

First claim

What is claimed is:

1 . A semiconductor structure, comprising:
a base substrate; an oxide layer over the base substrate; a semiconductor layer over the oxide layer; an insulating pillar extending through the semiconductor layer and the oxide layer and into the base substrate, wherein the insulating pillar includes a composition different than the oxide layer and wherein the insulating pillar has a sidewall having the composition and interfacing the oxide layer, the semiconductor layer, and the base substrate; an epitaxial layer on the semiconductor layer, wherein fin elements are formed within the epitaxial layer-such that the epitaxial layer extends from interfacing the semiconductor layer to an upper surface of the fin element; wherein a protrusion of the oxide layer extends through the semiconductor layer at a first region spaced a distance from the insulating pillar, and wherein the fin elements are disposed above and laterally spaced from the insulating pillar and the protrusion of oxide in a cross-sectional view such that an isolation region that extending between the fin elements is disposed above and vertically aligned with the insulating pillar and the protrusion of oxide.

2 . The semiconductor structure of claim 1 , wherein the composition of the insulating pillar comprises silicon nitride.

3 . The semiconductor structure of claim 1 wherein the semiconductor layer is silicon.

4 . The semiconductor structure of claim 1 , wherein the epitaxial layer is disposed directly on the semiconductor layer and wherein a first void interposes the epitaxial layer and the insulating pillar and a second void interposes the epitaxial layer and the protrusion of the oxide layer, wherein the first void and the second void are not directly underneath the fin elements.

5 . The semiconductor structure of claim 1 , wherein the insulating pillar extending into the base substrate has a cross-sectional view of a triangular shape.

6 . The semiconductor structure of claim 1 , wherein the insulating pillar has a top view with a circular-shape.

7 . The semiconductor structure of claim 1 , wherein from a top view a rectangular portion of the semiconductor structure includes a first insulating pillar at a first corner and a second insulating pillar at a second corner, a third insulating pillar at a third corner and a fourth insulating pillar at a fourth corner, wherein the fin elements are disposed between the first, second, third and fourth insulating pillars in the top view.

8 . The semiconductor structure of claim 7 , wherein the oxide layer has a plurality of raised portions extending through the semiconductor layer, wherein the plurality of raised portions are, in the top view, disposed in a region between the first, second, third, and fourth insulating pillars.

9 . A semiconductor device, comprising:
a silicon-on-insulator (SOI) structure, wherein the SOI structure includes:
a base substrate;
an oxide layer over the base substrate;
a semiconductor layer over the oxide layer; and
a dielectric feature extending from a top surface of the base substrate to a top surface of the semiconductor layer, wherein the dielectric feature is one of at least four dielectric features arranged in an array in a top view;
wherein each of the at least four dielectric features is vertically aligned under an isolation feature disposed on the semiconductor layer and wherein active regions of the semiconductor layer extend above the isolation feature, the isolation feature extending between active regions;
an epitaxial layer over the SOI structure, the epitaxial layer interfaces a top surface of the semiconductor layer and extends above the semiconductor layer; and
a field effect transistor (FET) formed over the SOI structure, wherein the FET includes a gate structure formed over a channel region disposed in the epitaxial layer, the channel region being laterally offset from the dielectric feature and the gate structure extending vertically over the dielectric feature.

10 . The semiconductor device of claim 9 , wherein the dielectric feature is a circular shape in a top view.

11 . The semiconductor device of claim 9 , wherein the dielectric feature is a nitride composition.

12 . The semiconductor device of claim 11 , wherein the nitride composition is SiCN.

13 . The semiconductor device of claim 9 , further comprising: an epitaxial layer over the semiconductor layer and the dielectric feature, wherein a void interposes the epitaxial layer and the dielectric feature.

14 . The semiconductor device of claim 9 , wherein the isolation feature is a shallow trench isolation feature extends between and adjacent the fin elements that provide the active regions, and wherein the each of the at least four dielectric features is vertically aligned with the shallow trench isolation feature.

15 . A semiconductor structure, comprising:
an insulating layer having a first composition on a base substrate; a semiconductor layer formed on the insulating layer; a dielectric support structure having a second composition and extending through the insulating layer and the semiconductor layer, the dielectric support structure having an upper surface; a void disposed on the upper surface of the dielectric support structure, the void surrounded by an epitaxial layer over the semiconductor layer and the upper surface of the dielectric support structure; and wherein the insulating layer includes a raised portion extending through the semiconductor layer and spaced a distance from the dielectric support structure, wherein vertically aligned with the raised portion is an indentation in the base substrate; a first active region and a second active region over the semiconductor layer, wherein in a cross-sectional view, the first active region and the second active region are between the raised portion and the dielectric support structure; and an isolation feature disposed over the semiconductor layer, the dielectric support structure, the void, and the raised portion of the insulating layer.

16 . The semiconductor structure of claim 15 , further comprising:
an epitaxial layer disposed over the semiconductor layer, the first active region and the second active region each including fin structures extending from the epitaxial layer.

17 . The semiconductor structure of claim 15 , wherein the void has a triangular shape in the cross-sectional view, and wherein the indentation in the base substrate has a triangular shape.

18 . The semiconductor structure of claim 17 , wherein a base of the triangular shape is defined by the upper surface of the dielectric support structure.

19 . The semiconductor structure of claim 15 , wherein the semiconductor layer has a Si ( 111 ) plane interfacing the epitaxial layer.

20 . The semiconductor structure of claim 15 , wherein the raised portion of the insulating layer has a circular shape in a top view and the dielectric support structure has a circular shape in the top view.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chu Feng-Ching
• Wong I-Hsieh
• Lee Wei-Yang
• Lin Chia-Pin

Classifications

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title

• H10P14/6306

  of the semiconductor materials · CPC title

• H10D86/011

  comprising FinFETs · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title