Three-dimensional memory device containing composite word lines including a respective fluorine-free capping sublayer and methods of forming the same

Patent metadata

Field	Value
Publication number	US-12588209-B2
Application number	US-202318360474-A
Country	US
Kind code	B2
Filing date	Jul 27, 2023
Priority date	Mar 7, 2023
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

A method of forming a memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming memory openings through the alternating stack, forming memory opening fill structures in the memory openings including respective vertical stack of memory elements and a respective vertical semiconductor channel, forming a lateral isolation trench through the alternating stack, forming lateral recesses by removing the sacrificial material layers selective to the insulating layers and the memory opening fill structures, depositing a first tungsten layer in the lateral recesses using a first tungsten deposition process in which a fluorine-containing tungsten precursor gas is used as a reactant, and depositing a second tungsten layer on the first tungsten layer in the lateral recesses using a second tungsten deposition process in which a fluorine-free tungsten precursor gas is used as a reactant.

First claim

What is claimed is:

1 . A method of forming a memory device, comprising:
forming an alternating stack of insulating layers and sacrificial material layers over a substrate; forming memory openings through the alternating stack; forming memory opening fill structures in the memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements and a respective vertical semiconductor channel; forming a lateral isolation trench through the alternating stack; forming lateral recesses by removing the sacrificial material layers selective to the insulating layers and the memory opening fill structures; depositing a first tungsten layer in the lateral recesses using a first tungsten deposition process in which a fluorine-containing tungsten precursor gas is used as a reactant; and depositing a second tungsten layer on the first tungsten layer in the lateral recesses using a second tungsten deposition process in which a fluorine-free tungsten precursor gas is used as a reactant.

2 . The method of claim 1 , further comprising depositing a conductive metallic barrier liner in the lateral recesses prior to the depositing the first tungsten layer in the lateral recesses, wherein the first tungsten layer is deposited on the conductive metallic barrier liner located in the lateral recesses.

3 . The method of claim 1 , wherein the first tungsten deposition process comprises tungsten deposition using tungsten hexafluoride as the reactant.

4 . The method of claim 1 , wherein:
the second tungsten deposition process comprises multiple repetitions of a unit processing sequence; and the unit processing sequence comprises a reactant soak step in which the fluorine-free tungsten precursor gas is provided into the lateral recesses, a first purge step, a reduction step in which a reducing gas is provided into the lateral recesses, and a second purge step.

5 . The method of claim 4 , wherein:
the fluorine-free tungsten precursor gas comprises WCl 5 , WO 2 Cl 2 or WOCl 4 ; and the reducing gas comprises hydrogen.

6 . The method of claim 5 , wherein nitrogen purge gas is provided into the lateral recesses during the first and the second purge steps.

7 . The method of claim 1 , further comprising prior to the depositing the second tungsten layer, exposing an outer surface of the first tungsten layer to an oxygen containing ambient to oxidize the outer surface of the first tungsten layer followed by annealing the first tungsten layer in an inert ambient to remove at least one of tungsten oxide or tungsten oxyfluoride from the outer surface of the first tungsten layer.

8 . The method of claim 1 , wherein the second tungsten layer encloses an encapsulated cavity that is free of any solid-phase material and is laterally surrounded by a subset of the memory opening fill structures.

9 . The method of claim 1 , wherein the second tungsten layer contains at least 50% less fluorine than the first tungsten layer.

10 . The method of claim 1 , wherein a surface portion of the first tungsten layer comprises boron or silicon at a peak atomic concentration in a range from 1 part per million to 10,000 parts per million, and the second tungsten layer is free of silicon and boron atoms or comprises silicon or boron atoms at an average atomic concentration less than 1 part per million.

Assignees

• Sandisk Technologies Llc
• Sandisk Technologies Inc

Inventors

• Mukae Yusuke
• Hinoue Tatsuya
• Makala Raghuveer S
• Asaeda Shungo

Classifications

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title

• H10B41/10

  characterised by the top-view layout · CPC title

• H10B41/50

  characterised by the boundary region between the core region and the peripheral circuit region · CPC title