Semiconductor device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-12588191-B2
Application number	US-202318241989-A
Country	US
Kind code	B2
Filing date	Sep 4, 2023
Priority date	Apr 23, 2023
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

The present disclosure provides a semiconductor memory device and a method of fabricating the same, including a substrate, a plurality of bit lines, a bit line contact, a spacer, a liner layer, and a storage node contact. The bit lines are separately disposed on the substrate. The bit line contact is disposed below one of the bit lines to extend into one active area. The spacer is disposed on sidewalls of each of the bit lines and the bit line contact. The liner layer is disposed on the substrate along an outer periphery of the bit line contact, wherein the liner layer comprises a first portion embedded in the one of the bit line, between the bit line contact and the one of the bit lines in an extending direction of the bit lines. The storage node contact and the bit lines are alternately arranged with each other.

First claim

What is claimed is:

1 . A semiconductor memory device, comprising:
a substrate, comprising a plurality of active areas and a shallow trench isolation; a plurality of bit lines, separately disposed on the substrate; a bit line contact, disposed below one of the bit lines to extend into one of the active areas; a spacer, disposed on sidewalls of the bit lines and the bit line contact; a liner layer, disposed on the substrate along an outer periphery of the bit line contact, wherein the liner layer comprises a first portion embedded in the one of the bit line, and the first portion is disposed between the bit line contact and the one of the bit lines in an extending direction of the bit lines; and a storage node contact, disposed on the one of the active areas, the storage node contact and the bit lines are alternately arranged with each other.

2 . The semiconductor memory device according to claim 1 , wherein the liner layer further comprises a second portion disposed between the bit line contact and the storage node contact.

3 . The semiconductor memory device according to claim 2 , wherein a portion of the spacer is disposed on the second portion.

4 . The semiconductor memory device according to claim 1 , wherein the liner layer directly contacts the shallow trench isolation in the substrate.

5 . The semiconductor memory device according to claim 1 , further comprising:
a dielectric layer, disposed on the substrate, between the bit lines and the substrate, wherein the liner layer directly contacts a top surface of the dielectric layer.

6 . The semiconductor memory device according to claim 2 , wherein the liner layer is disposed around the bit line contact, and includes an insulating material which is different from that of the shallow trench isolation.

7 . The semiconductor memory device according to claim 1 , wherein each of the bit lines comprises a bottom semiconductor layer, a barrier layer and a conductive layer stacked sequentially from bottom to top, and a top surface of the liner layer is higher than a top surface of the bottom semiconductor layer of each of the bit lines.

8 . The semiconductor memory device according to claim 2 , wherein a top surface of the first portion is higher than a top surface of the second portion.

9 . A semiconductor memory device, comprising:
a substrate, comprising a plurality of active areas and a shallow trench isolation; a plurality of bit lines, separately disposed on the substrate, each of the bit lines comprises a conductive layer and a capping layer stacked from bottom to top, and a top portion of the capping layer comprises a plurality of protrusions; a bit line contact, disposed below one of the bit lines to extend into one of the active areas, wherein one of the protrusions is disposed around the bit line contact; a spacer, disposed on sidewalls of each of the bit lines and the bit line contact; and a storage node contact, disposed on the one of the active areas, the storage node contact and the bit lines are alternately arranged with each other.

10 . The semiconductor memory device according to claim 9 , further comprising:
a liner layer, disposed on the substrate along an outer periphery of the bit line contact, wherein the one of the protrusions overlaps the liner layer.

11 . The semiconductor memory device according to claim 10 , wherein the liner layer is partially embedded in the one of the bit lines.

12 . The semiconductor memory device according to claim 10 , wherein the liner layer is partially sandwiched between the spacer disposed on the bit line contact and the storage node contact.

13 . A method of fabricating a semiconductor memory device, comprising:
providing a substrate, comprising a plurality of active areas and a shallow trench isolation; forming a plurality of bit lines separately disposed on the substrate; forming a bit line contact below one of the bit lines, the bit line contact being extended into one of the active areas; forming a spacer on sidewalls of each of the bit lines and the bit line contact; forming a liner layer on the substrate along an outer periphery of the bit line contact, wherein the liner layer comprises a first portion embedded in the one of the bit line, and the first portion is disposed between the bit line contact and the one of the bit lines in an extending direction of the bit lines; and forming a storage node contact on the one of the active areas, the storage node contact and the bit lines are alternately arranged with each other.

14 . The method of fabricating the semiconductor memory device according to claim 13 , wherein the liner layer further comprises a second portion disposed between the bit line contact and the storage node contact.

15 . The method of fabricating the semiconductor memory device according to claim 13 , further comprising:
forming a dielectric layer on the substrate; forming a sacrificial layer on the dielectric layer, the sacrificial layer comprising an opening formed therein; forming a liner material layer on the substrate, covering the sacrificial layer and a surface of the opening; partially removing the substrate, to form a contact opening in the substrate; and partially removing the liner material layer, to form the liner layer.

16 . The method of fabricating the semiconductor memory device according to claim 15 , wherein after partially removing the dielectric layer, forming the liner material layer.

17 . The method of fabricating the semiconductor memory device according to claim 15 , wherein before partially removing the dielectric layer, forming the liner material layer.

18 . The method of fabricating the semiconductor memory device according to claim 15 , further comprising:
forming a dielectric material layer on the substrate, to fill in a space between each of the bit lines; partially removing the dielectric material layer, to form a plurality of plug openings, to exposed each of the active areas; and forming the storage node contact in each of the plug openings.

19 . The method of fabricating the semiconductor memory device according to claim 18 , further comprising:
while forming the plug openings, removing the second portion of the liner layer between the bit line contact and the storage node contact, wherein the liner layer comprises a material the same as that of the shallow trench isolation.

20 . The method of fabricating the semiconductor memory device according to claim 14 , further comprising:
forming a plurality of word lines in the substrate; and forming a plurality of word-line isolating layers on the substrate to aligned with each of the word lines, wherein the second portion of the liner layer is formed between adjacent ones of the word-line isolating layer, and comprises a material the same as that of the word-line isolating layer.

Assignees

• Fujian Jinhua Integrated Circuit Co Ltd

Inventors

• Zhang Janbo

Classifications

• H10B12/485

  Bit line contacts · CPC title

• H10B12/0335 Primary

  Making a connection between the transistor and the capacitor, e.g. plug · CPC title

• H10B12/315

  with the capacitor higher than a bit line · CPC title

• H10B12/482 Primary

  Bit lines · CPC title