GDDR memory expander using CMT connector

Patent metadata

Field	Value
Publication number	US-12588149-B2
Application number	US-202217871542-A
Country	US
Kind code	B2
Filing date	Jul 22, 2022
Priority date	Jun 3, 2022
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

Methods and apparatus for GDDR (Graphics Double Date Rate) memory expander using compression mount technology (CMT) connectors. A CMT connector with a dedicated pinout for GDDR-based memory is provided that enables end users and manufacturers to change the amount of GDDR memory provided with a GPU card, accelerator card, or apparatus having other form factors. Memory could also be replaced in the event of a failure. In addition, embodiments are disclosed that support a split channel concept where there could be multiple devices (e.g., GDDR modules) with dedicated signals routed to each module.

First claim

What is claimed is:

1 . A card comprising:
a printed circuit board (PCB) having a plurality of components and circuitry mounted or operationally coupled thereto and including one or more arrays of compression mount technology (CMT) contact pads; a processor, operatively coupled to the PCB, the processor having pins or pads that are electrically coupled to CMT contact pads in the one or more arrays of CMT contact pads via wiring in the PCB; and one or more CMT Graphic Double Data Rate (GDDR) modules, each including a plurality of GDDR memory devices mounted to a substrate, the GDDR memory devices communicatively coupled via wiring in the substate to an array of CMT contact pads formed on an underside of the substrate; wherein each of the one or more CMT GDDR modules is communicatively coupled to the PCB via a respective CMT connector interposed between the CMT GDDR module and the PCB proximate to an array of CMT contact pads on the PCB.

2 . The card of claim 1 , wherein a CMT connector has an array of spring-loaded pins, and wherein for each of at least a portion of the spring-loaded pins in the array, a contact at a first end of the pin is in compression contact with a respective CMT contact pad on the substrate of a CMT GDDR module and a contact on an opposing end of the pin is in contact with a respective CMT contact pad on the PCB.

3 . The card of claim 1 , wherein the processor comprises a Graphics Processor Unit (GPU).

4 . The card of claim 1 , wherein the processor comprises one of a Tensor Processing Unit (TPU), Data Processing Unit (DPU), Infrastructure Processing Unit (IPU), Artificial Intelligence (AI) processor, AI inference unit, or a Field Programmable Gate Array (FPGA).

5 . The card of claim 1 , wherein the GDDR memory devices comprise GDDR5 or GDDR6 SDRAM devices.

6 . The card of claim 1 , wherein the GDDR memory devices comprise GDDR6+or GDDR7 SDRAM devices.

7 . The card of claim 1 , wherein the substrate for a CMT GDDR module is mounted to the PCB via at least one pair of fasteners.

8 . An apparatus, comprising:
a printed circuit board (PCB) having a plurality of components and circuitry mounted or operationally coupled thereto and including one or more arrays of compression mount technology (CMT) contact pads; a processor, operatively coupled to the PCB, the processor having pins or pads that are electrically coupled to CMT contact pads in the one or more arrays of CMT contact pads via wiring in the PCB; and a first CMT Graphic Double Data Rate (GDDR) module including a plurality of GDDR memory devices and an on module CMT connector; a CMT connector interposed between the first CMT GDDR module and the PCB proximate to the one or more arrays of CMT contact pads on the PCB; and a second CMT GDDR module, operatively coupled to the on module CMT connector of the first CMT GDDR module.

9 . The apparatus of claim 8 , wherein the processor comprises a Graphics Processor Unit (GPU).

10 . The apparatus of claim 8 , wherein the processor is another processing unit (XPU) comprising one of a Tensor Processing Unit (TPU), Data Processing Units (DPU), Infrastructure Processing Unit (IPU), Artificial Intelligence (AI) processor, AI inference units, or a Field Programmable Gate Array (FPGA).

11 . The apparatus of claim 8 , wherein the GDDR memory devices comprise GDDR5, GDDR6, GDDR6+or GDDR7 SDRAM devices.

12 . The apparatus of claim 8 wherein the first CMT GDDR module comprises:
a substrate to which GDDR memory devices in the plurality of GDDR memory devices are mounted, the substrate having first and second arrays of CMT contact pads on an underside thereof;
first wiring in the substrate communicatively coupling the GDDR memory devices to CMT contact pads in the first array of CMT contact pads;
the on module CMT connector having an array of spring-loaded contacts, mounted to the first substrate; and
second wiring in the substrate coupling spring-loaded contacts in the array of spring-loaded contacts to CMT contact pads in the second array of CMT contact pads.

13 . The apparatus of claim 9 , wherein the second CMT GDDR module has a configuration similar to the first CMT GDDR module including an on module CMT connector.

14 . The apparatus of claim 9 , wherein the second CMT GDDR module does not include an on module CMT connector.

15 . The apparatus of claim 9 , wherein the CMT connector has an array of spring-loaded pins, and wherein for each of at least a portion of the spring-loaded pins in the array, a contact at a first end of the pin is in compression contact with a respective CMT contact pad on the substrate of the first CMT GDDR module and a contact on an opposing end of the pin is in contact with a respective CMT contact pad on the PCB.

16 . An apparatus, comprising:
a substrate to which multiple GDDR memory devices are mounted, the substrate having first and second arrays of CMT contact pads on an underside thereof; first wiring in the substrate communicatively coupling the GDDR memory devices to CMT contact pads in the first array of CMT contact pads; an on module CMT connector mounted to the substrate and having an array of spring-loaded contacts or pins extending above a top surface thereof; and second wiring in the substrate coupling the spring-loaded contacts or pins to CMT contact pads in the second array of CMT contact pads.

17 . The apparatus of claim 16 , wherein the spring-loaded contacts or pins include or are operatively coupled to conductive members extending downward below the on module CMT connector, and wherein the on module CMT connector is coupled to the substrate via an array of solder balls that are formed around the conductive members.

18 . The apparatus of claim 16 , wherein the GDDR memory devices comprise GDDR5, GDDR6, GDDR6+or GDDR7 SDRAM devices.

19 . The apparatus of claim 16 , wherein the substrate comprises a printed circuit board.

20 . The apparatus of claim 16 , wherein the substrate has a first pair of holes passing through the substate toward a first end and a second pair of holes passing through the substrate toward a second end.

Assignees

• Intel Corp

Inventors

• Li Xiang
• Ganguly Konika
• Zhai Tongyan
• Vergis George
• Constantine Anthony M
• Liao Jun

Classifications

• H05K1/116

  Lands, clearance holes or other lay-out details concerning the surrounding of a via · CPC title

• H05K2201/10159

  Memory · CPC title

• H01R13/2407

  characterized by the resilient means · CPC title

• H01R12/7082

  Coupling device supported only by cooperation with PCB · CPC title

• H05K2201/10409

  Screws · CPC title