Low profile SODIMM (small outline dual inline memory module)

Patent metadata

Field	Value
Publication number	US-12349274-B2
Application number	US-202117354540-A
Country	US
Kind code	B2
Filing date	Jun 22, 2021
Priority date	Jun 22, 2021
Publication date	Jul 1, 2025
Grant date	Jul 1, 2025

Abstract

A memory module has pads on the top and bottom surfaces of a module printed circuit board (PCB). The pads match the pin layout of one or more memory devices to be mounted on the memory module. The pads on one surface of the PCB electrically interconnect to the memory device(s), and the pads on the other surface electrically interconnect to pads on a system board, such as a motherboard. With the pad layout on the memory module, the pad layout of the system board can be the same for a memory-down implementation and for a removable memory module. The pad layout provides good signal-to-noise performance and can enable a memory module for low power double data rate (LPDDR) memory, double data rate (DDR) memory, and graphics double data rate (GDDR) memory.

First claim

What is claimed is:

1. A memory module, comprising:
a first printed circuit board (PCB) surface including a first pad layout matching a pin layout of a contact array of a memory chip package of a memory chip, to electrically interconnect to the memory chip; and
a second PCB surface opposite the first PCB surface, the second PCB surface including a second pad layout matching the pin layout of the memory chip package, the second pad layout having spring structures to electrically interconnect to a matching pad layout on a system board, the spring structures to compress when the memory module is mounted to the system board.

2. The memory module of claim 1 , wherein the second pad layout is electrically connected with the first pad layout with through-hole connectors, without routing traces between corresponding pads.

3. The memory module of claim 1 , wherein the matching pad layout on the system board includes a compression-based contact corresponding to each pad, wherein pads of the second pad layout physically contact corresponding compression-based contacts of the matching pad layout on the system board.

4. The memory module of claim 1 , wherein the second PCB surface includes a compression-based contact corresponding to each pad, wherein pads of the matching pad layout of the system board physically contact corresponding compression-based contacts of the second pad layout.

5. The memory module of claim 1 , wherein the memory chip comprises a first memory chip;
wherein the first PCB surface further comprises a third pad layout matching a pin layout of a second memory chip package of a second memory chip, to electrically interconnect to the second memory chip; and
wherein the second PCB surface comprises a fourth pad layout matching the pin layout of the second memory chip, the fourth pad layout to electrically interconnect to a matching pad layout on a system board.

6. The memory module of claim 1 , wherein the system board comprises a motherboard.

7. The memory module of claim 1 , wherein the first PCB surface and the second PCB surface comprise surfaces of a 2-layer PCB.

8. The memory module of claim 1 , wherein the memory chip comprises a dynamic random access memory (DRAM) device compatible with a double data rate (DDR) standard.

9. The memory module of claim 8 , wherein the DRAM device comprises a DRAM device compatible with a low power double data rate (LPDDR) standard.

10. A computer system comprising:
a system board including a system pad layout matching a pin layout of a memory chip package of a memory chip;
a memory module including:
the memory chip mounted to a first pad layout of a first printed circuit board (PCB) surface, the first pad layout matching the pin layout of the memory chip package; and
a second PCB surface opposite the first PCB surface, the second PCB surface including a second pad layout matching the pin layout of the memory chip package, the second pad layout to electrically interconnect to a matching pad layout on a system board; and

a contact assembly having an array of contacts matching the pin layout of the memory chip package, the contact assembly disposed between the system board and the memory module to electrically interconnect the second pad layout with the system pad layout, wherein the array of contacts comprises a spring structure to contact each pad of the system pad layout.

11. The computer system of claim 10 , wherein the second pad layout is electrically connected with the first pad layout with through-hole connectors, without routing traces between corresponding pads.

12. The computer system of claim 10 , wherein the array of contacts further comprises a spring structure to contact each pad of the second pad layout.

13. The computer system of claim 10 , wherein the contact assembly is soldered directly on the system pad layout of the system board.

14. The computer system of claim 10 , wherein the contact assembly is soldered directly on the second pad layout of the memory module.

15. The computer system of claim 10 , wherein the contact assembly comprises a contact assembly of an interposer board to be removably disposed between the system board and the memory module.

16. The computer system of claim 10 , wherein the memory chip comprises a first memory chip;
wherein the first PCB surface further comprises a third pad layout matching a pin layout of a second memory chip package of a second memory chip, to electrically interconnect to the second memory chip; and
wherein the second PCB surface comprises a fourth pad layout matching the pin layout of the second memory chip package, the fourth pad layout to electrically interconnect to a matching pad layout on a system board.

17. The computer system of claim 10 , wherein the system board comprises a motherboard.

18. The computer system of claim 10 , further comprising:
screws to secure the memory module to the system board, including to secure the contact assembly to ensure electrical interconnection of the second pad layout with the system pad layout.

19. The computer system of claim 10 , wherein the system pad layout comprises a first system pad layout, the memory module comprises a first memory module, and the contact assembly comprises a first contact assembly, wherein the system board includes the first system pad layout on a first system board surface, and further comprising:
a second system pad layout on a second system board surface;
a second memory module; and
a second contact assembly to interconnect the second memory module to the second system pad layout.

20. The computer system of claim 10 , wherein the memory chip comprises a dynamic random access memory (DRAM) device compatible with a double data rate (DDR) standard.

21. The computer system of claim 20 , wherein the DRAM device comprises a DRAM device compatible with a low power double data rate (LPDDR) standard.

22. The computer system of claim 10 , further comprising one or more of:
a host processor device mounted on the system board;
a display communicatively coupled to a host processor of the system board;
a network interface communicatively coupled to a host processor of the system board; or
a battery to power the computer system.

Assignees

• Intel Corp

Inventors

• Rao Raghavendra
• Balakrishnan Ranjul
• Chauhan Shailendra Singh
• Geejagaaru Sandesh Krishnamurthy

Classifications

• H05K1/141 Primary

  One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters (H05K1/142 and H05K1/147 take precedence) · CPC title

• H05K2201/10159

  Memory · CPC title

• H05K2201/10545

  Related components mounted on both sides of the PCB · CPC title

• H05K2201/10674

  Flip chip · CPC title

• H05K2201/0311

  Metallic part with specific elastic properties, e.g. bent piece of metal as electrical contact · CPC title