Signal transceiver, die and device

Patent metadata

Field	Value
Publication number	US-12587173-B2
Application number	US-202418637228-A
Country	US
Kind code	B2
Filing date	Apr 16, 2024
Priority date	Apr 16, 2024
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

A signal transceiver includes a driver, an interference removal circuit and a split-termination resistor. The interference removal circuit includes a first passive circuit and a second passive circuit. The interference removal circuit has a first port connected to an output terminal of the driver, for receiving an outbound signal output by the driver. The interference removal circuit has a second port used to output the outbound signal and receive an inbound signal. The interference removal circuit has a third port and a fourth port that are used to output a recovery signal, where the recovery signal is the inbound signal after an interference caused by the outbound signal removed by the first passive circuit and the second passive circuit. The split-termination resistor is connected between the first port and the second port. The first passive circuit is connected between the first port and the third port, and the second passive circuit is connected between the second port and the fourth port.

First claim

What is claimed is:

1 . A signal transceiver, comprising:
a driver; an interference removal circuit, including a first passive circuit and a second passive circuit, wherein
the interference removal circuit has a first port connected to an output terminal of the driver, for receiving an outbound signal output by the driver;
the interference removal circuit has a second port used to output the outbound signal and receive an inbound signal; and
the interference removal circuit has a third port and a fourth port that are used to output a recovery signal, wherein the recovery signal is the inbound signal after an interference caused by the outbound signal is removed by the first passive circuit and the second passive circuit, wherein
the first passive circuit is connected between the first port and the third port, and the second passive circuit is connected between the second port and the fourth port; and
a split-termination resistor, connected between the first port and the second port.

2 . The signal transceiver according to claim 1 , wherein
the first passive circuit includes a first component module and a second component module, wherein
the first component module is connected between the first port and the third port, and the first component module includes a first adjustable capacitor and a first series circuit connected in parallel with the first adjustable capacitor; the first series circuit includes a first adjustable resistor and a first capacitor that are connected in series; and
the second component module is connected between the third port and a ground of the first passive circuit, and the second component module includes a second adjustable capacitor and a second series circuit connected in parallel with the second adjustable capacitor; the second series circuit includes a second adjustable resistor and a second capacitor that are connected in series; and
the second passive circuit includes a third component module and a fourth component module, wherein
the third component module is connected between the second port and the fourth port, and the third component module includes a third adjustable capacitor and a third series circuit connected in parallel with the third adjustable capacitor; the third series circuit includes a third adjustable resistor and a third capacitor that are connected in series; and
the fourth component module is connected between the fourth port and a ground of the second passive circuit, and the fourth component module includes a fourth adjustable capacitor and a fourth series circuit connected in parallel with the fourth adjustable capacitor; the fourth series circuit includes a fourth adjustable resistor and a fourth capacitor that are connected in series.

3 . The signal transceiver according to claim 2 , wherein the first component module and the second component module are connected to a common-mode voltage source through an adjustable resistor, and the third component module and the fourth component module are connected to the common-mode voltage source through another adjustable resistor.

4 . The signal transceiver according to claim 1 , wherein a signal transfer function of the first passive circuit and a signal transfer function of the second passive circuit satisfy:

H
2

(
s
)

=

H
1

(
s
)

⁢

(

1
+

R
sp

Z
T

)

;

wherein H 2 (s) is the signal transfer function of the second passive circuit, H 1 (s) is the signal transfer function of the first passive circuit, R sp is a resistance value of the split-termination resistor, and Z T is a sum of an output impedance value of the driver and the resistance value of the split-termination resistor.

5 . The signal transceiver according to claim 1 , wherein a signal transfer function of the first passive circuit is one that maximizes a worst-case eye height of the recovery signal in a case where a high-level signal is sent to the signal transceiver.

6 . The signal transceiver according to claim 1 , wherein a resistance value of an output resistor of the driver is greater than a resistance value of the split-termination resistor.

7 . The signal transceiver according to claim 1 , wherein the driver includes a pre-driver, an output driver, and a programmable feedback resistor, wherein
a signal output terminal of the pre-driver is connected to a signal input terminal of the output driver, and the programmable feedback resistor is connected between the signal input terminal and a signal output terminal of the output driver; the output driver includes a complementary metal-oxide semiconductor (CMOS) inverter, and an output impedance of the output driver is equal to a reciprocal of transconductance of the CMOS inverter; and the pre-driver is used to output a current signal to the output driver, and the output driver is used to convert the current signal into a voltage signal as the outbound signal for output.

8 . The signal transceiver according to claim 1 , wherein a sum of an output impedance of the driver and a resistance value of the split-termination resistor is equal to a value of characteristic impedance of a transmission line connected to the second port.

9 . A die, comprising at least one signal transceiver, each signal transceiver of the at least one signal transceiver including:
a driver; an interference removal circuit, including a first passive circuit and a second passive circuit, wherein
the interference removal circuit has a first port connected to an output terminal of the driver, for receiving an outbound signal output by the driver;
the interference removal circuit has a second port used to output the outbound signal and receive an inbound signal; and
the interference removal circuit has a third port and a fourth port that are used to output a recovery signal, wherein the recovery signal is the inbound signal after an interference caused by the outbound signal is removed by the first passive circuit and the second passive circuit, wherein
the first passive circuit is connected between the first port and the third port, and the second passive circuit is connected between the second port and the fourth port; and
a split-termination resistor, connected between the first port and the second port.

10 . The die according to claim 9 , wherein
the first passive circuit includes a first component module and a second component module, wherein
the first component module is connected between the first port and the third port, and the first component module includes a first adjustable capacitor and a first series circuit connected in parallel with the first adjustable capacitor; the first series circuit includes a first adjustable resistor and a first capacitor that are connected in

Assignees

• Huawei Tech Canada Co Ltd
• Governing Council Univ Toronto

Inventors

• Jarrett-Amor Durand Philippe
• Chan Carusone Anthony
• Jalali Mohammad Sadegh

Classifications

• H03H11/04 Primary

  Frequency selective two-port networks · CPC title