Self-interference, echo and crosstalk mitigation in multi-lane interconnects

Patent metadata

Field	Value
Publication number	US-2024348285-A1
Application number	US-202418633022-A
Country	US
Kind code	A1
Filing date	Apr 11, 2024
Priority date	Apr 11, 2023
Publication date	Oct 17, 2024
Grant date	—

Abstract

Embodiments disclosed herein provides a method for mitigating an interference signal in a multi-lane interconnect. The method includes transmitting, by a first device ( 101 ), a first signal using a MLD ( 504 ) to a second device ( 103 ) on a first transmission line of the multi-lane interconnect between the first device ( 101 ) and the second device ( 102 ). The method includes receiving a second signal transmitted from the second device ( 102 ) on the first transmission line while simultaneously transmitting the first signal to the second device ( 102 ) on the first transmission line. Further, the method includes adjusting the plurality of impedances such that an input impedance (Zin) seen into the first device from the first transmission line matches the characteristic impedance (Z 0 ) of the first transmission line. One or more transconductance cells or driver cells in the RD are tuned for cancellation or suppression of interference signals at a RFE ( 505 ) input.

First claim

What is claimed is:

1 . A method for mitigating an interference signal in a multi-lane interconnect comprising:
transmitting, by a first device ( 101 ), a first signal using a Main Line Driver (MLD) ( 501 ) to a second device ( 103 ) on a first transmission line of the multi-lane interconnect between the first device ( 101 ) and the second device ( 103 ), wherein the multi-lane interconnect is associated with one of a single-ended transmission line circuit ( 205 a ) and differential-ended transmission line circuit ( 205 b ) between the first device ( 101 ) and the second device ( 103 ); receiving, by the first device ( 101 ), a second signal transmitted from the second device ( 103 ) on the first transmission line while simultaneously transmitting the first signal to the second device ( 103 ) on the first transmission line, wherein a signal at a Receiver Frontend (RFE) ( 505 ) input of the first device ( 101 ) comes through a ratioed impedance circuit of the first device ( 101 ) and comprises the second signal and the interference signal; adjusting, by the first device ( 101 ), a plurality of impedances such that an input impedance (Z in ) seen into the first device ( 101 ) from the first transmission line matches a characteristic impedance (Z 0 ) of the first transmission line; and tuning, by the first device ( 101 ), a Ratioed Driver (RD) ( 503 ) of the first device ( 101 ) to cancel or suppress at least a Self-Interference (SI) at the RFE ( 505 ) input of the first device ( 101 ) caused by the first signal.

2 . The method as claimed in claim 1 , wherein echoes of the first signal are also suppressed by the RD ( 503 ) by generating delayed replicas of the first signal, and scaling and adding the delayed replicas to the RFE ( 505 ) input of the first device ( 101 ).

3 . The method as claimed in claim 1 , wherein a Near End Cross Talk (NEXT) caused by at least one of the signals transmitted in adjacent lanes are also suppressed by the RD ( 503 ) by generating at least one of the original, and delayed replicas of the signals transmitted in the adjacent lane, and scaling and adding the generated signals to the RFE ( 505 ) input of the first device ( 101 ).

4 . The method as claimed in claim 1 , wherein the MLD ( 501 ) circuit comprises a plurality of transconductance cells or driver cells each of which is driven by a signal to be transmitted or the signal's delayed replica, wherein the transconductance cells or driver cells are tunable.

5 . The method as claimed in claim 1 , wherein the MLD ( 501 ) circuit is configured to transmit a Pulse Amplitude Modulation (PAM) signal with two bits represented by a Most Significant Bit (MSB) and Least Significant Bit (LSB).

6 . The method as claimed in claim 1 , wherein the RD ( 503 ) circuit provides a lower current or a lower power than the MLD ( 501 ) circuit to generate the RD ( 503 ) output to cancel or suppress the SI.

7 . The method as claimed in claim 1 , wherein the first device ( 101 ) performs transmit side pre-emphasis equalization by generating the signal to be transmitted and its delayed replicas using multiple transconductance cells or driver cells in the MLD ( 501 ).

8 . The method as claimed in claim 1 , wherein cancelling or suppressing, by the first device ( 101 ), the interference signal at the RFE ( 505 ) input of the first device ( 101 ) comprises:
correlating, by the first device ( 101 ), the RFE ( 505 ) output with the at least one of the original and delayed replicas of the first signal to adjust one or more weight coefficients to tune the strengths of the one or more of the transconductance cells or driver cells in the RD ( 503 ) adaptively.

9 . The method as claimed in claim 1 , wherein cancelling or suppressing, by the first device ( 101 ), the interference signal at the RFE ( 505 ) input of the first device ( 101 ) also comprises:
correlating, by the first device ( 101 ), the RFE ( 505 ) output with the at least one of the original and the delayed replicas of the signal transmitted by the first device ( 101 ) in adjacent lanes to adjust the weight coefficients to tune the strengths of the one or more of the transconductance cells or driver cells in the RD ( 503 ) adaptively to cancel or suppress the NEXT.

10 . A system ( 401 ) for mitigating an interference signal in a multi-lane interconnect, comprises:
a first device ( 101 ) comprising a plurality of transceivers ( 301 a - 301 c ), and a ratioed impedance controller ( 403 ); a second device ( 103 ) comprising a plurality of transceivers ( 302 a - 302 c ), and a ratioed impedance controller ( 405 ); a multi-lane interconnect circuit connecting the first device ( 101 ) with the second device ( 103 ) using a multi-lane interconnect, wherein the multi-lane interconnect circuit is one of a single-ended transmission line circuit ( 205 a ) and differential-ended transmission line circuit ( 205 b ) between the first device ( 101 ) and the second device ( 103 ), wherein the multi-lane interconnect circuit is configured to transmit a first signal to the second device ( 103 ) on a first transmission line of the multi-lane interconnect; wherein the a ratioed impedance controller ( 403 ) of the first device ( 101 ) is configured to:
transmit the first signal using a Main Line Driver (MLD) ( 501 ) to the second device ( 103 ) on the first transmission line of the multi-lane interconnect between the first device ( 101 ) and the second device ( 103 );
receive a second signal transmitted from the second device ( 103 ) on the first transmission line while simultaneously transmitting the first signal to the second device ( 103 ) on the first transmission line, wherein a signal at a Receiver Frontend (RFE) ( 505 ) input of the first device ( 101 ) comes through a ratioed impedance circuit of the first device ( 101 ) and comprises the second signal and the interference signal;
adjust a plurality of impedances such that an input impedance (Z in ) seen into the first device ( 101 ) from the first transmission line matches a characteristic impedance (Z 0 ) of the first transmission line; and
tune a Ratioed Driver (RD) ( 503 ) of the first device ( 101 ) to cancel or suppress at least a Self-Interference (SI) at the RFE ( 505 ) input of the first device ( 101 ) caused by the first signal.

11 . The system ( 401 ) as claimed in claim 10 , wherein echoes of the first signal are also suppressed by the RD ( 503 ) by generating delayed replicas of the first signal, and scaling and adding the delayed replicas to the RFE ( 505 ) input of the first device ( 101 ).

12 . The system ( 401 ) as claimed in claim 10 , wherein a Near End Cross Talk (NEXT) caused by at least one of the signals transmitted in adjacent lanes are also suppressed by the RD ( 503 ) by generating at least one of the original, and delayed replicas of the signals transmitted in the adjacent lanes, and scaling and adding the generated signals to the RFE ( 505 ) input of the first device ( 101 ).

13 . The system ( 401 ) as claimed in claim 10 , wherein the MLD ( 501 ) circuit comprises a plurality of transconductance cells or driver cells each of which is driven by a signal to be transmitted or the signal's delayed replica, wherein the transconductance cells or driver cells are tunable.

14 . The system ( 401 ) as claimed in claim 10 , wherein the MLD ( 501 ) circuit is configured to transmit a Pulse Amplitude Modulation (PAM) signal with two bits represented by a Most Significant Bit (MSB) and Least Significant Bit (LSB).

15 . The system ( 401 ) as claimed in claim 10 , wherein the RD ( 503 ) circuit provides a lower cur

Assignees

• Indian Inst Technology Bombay

Inventors

• Gupta Shalabh
• Parulekar Ganpat Anant
• Goyal Sandeep

Classifications

• H04B3/487

  Testing crosstalk effects · CPC title

• H04B3/32 Primary

  Reducing cross-talk, e.g. by compensating · CPC title