Memory system, operating method of the memory system, and interface circuit of the memory system

Patent metadata

Field	Value
Publication number	US-12586645-B2
Application number	US-202418444848-A
Country	US
Kind code	B2
Filing date	Feb 19, 2024
Priority date	Feb 21, 2023
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

A memory system includes a memory device having a plurality of non-volatile memories, a buffer chip connected with each of the plurality of non-volatile memories, and a memory controller connected with the buffer chip and configured to provide a data strobe signal and a data signal to the buffer chip. The buffer chip includes a first loop coupled to a sampler circuit and configured to perform first monitoring on the data strobe signal and first duty correction on the data strobe signal based on the first monitoring, and a second loop coupled to a multiplexer and configured to, responsive to the first duty correction, perform second monitoring on the data strobe signal and second duty correction on the data strobe signal based on the second monitoring. The buffer chip is configured to store first and second duty correction information for at least one of the plurality of non-volatile memories.

First claim

What is claimed is:

1 . A memory system comprising:
a memory device comprising a plurality of non-volatile memories; a buffer chip connected with the plurality of non-volatile memories; and a memory controller connected with the buffer chip and configured to provide a data strobe signal and a data signal to the buffer chip, wherein the buffer chip comprises: a sampler circuit; a multiplexer; a first loop coupled to the sampler circuit and configured to perform first monitoring on the data strobe signal and perform first duty correction on the data strobe signal based on the first monitoring; and a second loop coupled to the multiplexer and configured to, responsive to the first duty correction, perform second monitoring on the data strobe signal and perform second duty correction on the data strobe signal based on the second monitoring; wherein the buffer chip is configured to store first duty correction information and second duty correction information for at least one of the plurality of non-volatile memories based on the first duty correction and the second duty correction, respectively.

2 . The memory system of claim 1 , wherein the memory device comprises:
a third loop configured to, responsive to the second duty correction, perform third monitoring on the data strobe signal and perform third duty correction on the data strobe signal based on the third monitoring; and a fourth loop configured to perform fourth duty correction on the data signal, and the memory device is configured to store third duty correction information and fourth duty correction information for at least one of the plurality of non-volatile memories based on the third duty correction and the fourth duty correction, respectively.

3 . The memory system of claim 2 , wherein the third loop and the fourth loop are configured to simultaneously perform the third duty correction on the data strobe signal and the fourth duty correction on the data signal.

4 . The memory system of claim 1 , wherein the buffer chip comprises:
a first switch configured to be closed to connect the first loop with the second loop and control a flow of the data strobe signal; and a second switch configured to be closed to connect the sampler circuit with the multiplexer and control a flow of the data signal, wherein the buffer chip is configured to, responsive to the first duty correction, close the first switch and the second switch.

5 . The memory system of claim 1 , wherein the buffer chip comprises:
a third switch configured to be closed to connect the second loop with the memory device and control a flow of the data strobe signal; and a fourth switch configured to be closed to connect the multiplexer with an output terminal of the buffer chip and control a flow of the data signal, wherein the buffer chip is configured to, responsive to the second duty correction, close the third switch and the fourth switch.

6 . The memory system of claim 1 , wherein the first loop comprises a first data strobe signal monitor, a first data strobe signal compensator, a first counter, and a first register,
the second loop comprises a second data strobe signal monitor, a second data strobe signal compensator, a second counter, and a second register, and the first register and the second register are configured to store the first duty correction information and the second duty correction information, respectively.

7 . The memory system of claim 2 , wherein the third loop comprises a third data strobe signal monitor, a third data strobe signal compensator, a third counter, and a third register,
the fourth loop comprises a data signal monitor, a data signal compensator, a fourth counter, and a fourth register, the data signal compensator is configured to perform compensation on the data signal based on a reference voltage, and the third register and the fourth register are configured to store the third duty correction information and the fourth duty correction information, respectively.

8 . The memory system of claim 1 , wherein, responsive to selecting at least one non-volatile memory from among the plurality of non-volatile memories,
the buffer chip is configured to provide data signal duty correction information and data strobe signal duty correction information for the at least one non-volatile memory that was selected.

9 . An operating method of a memory system including a buffer chip connected with each of a plurality of non-volatile memories of a memory device, and a memory controller connected with the buffer chip and configured to provide a data strobe signal and a data signal thereto, the operating method comprising:
performing first monitoring on the data strobe signal, and performing first duty correction on the data strobe signal based on the first monitoring; responsive to the first duty correction, performing second monitoring on the data strobe signal, and performing second duty correction on the data strobe signal based on the second monitoring; and storing first duty correction information and second duty correction information for at least one of the plurality of non-volatile memories based on the first duty correction and the second duty correction, respectively.

10 . The operating method of claim 9 , further comprising:
responsive to the second duty correction, performing third monitoring on the data strobe signal, and performing third duty correction on the data strobe signal based on the third monitoring; performing fourth duty correction on the data signal; and storing third duty correction information and fourth duty correction information for at least one of the plurality of non-volatile memories based on the third duty correction and the fourth duty correction, respectively.

11 . The operating method of claim 10 , wherein the performing of the third duty correction and the performing of the fourth duty correction comprise simultaneously performing the third duty correction and the fourth duty correction.

12 . The operating method of claim 9 , wherein the performing of the first duty correction comprises connecting a first loop with a second loop using a closed state of a first switch to control a flow of the data strobe signal,
the performing of the second duty correction comprises connecting a data signal sampler with a multiplexer using a closed state of a second switch to control a flow of the data signal, and the operating method further comprises, responsive to the first duty correction, operating the first switch and the second switch to the closed states, respectively.

13 . The operating method of claim 10 , wherein the performing of the third duty correction comprises connecting a second loop with the memory device using a closed state of a third switch to control a flow of the data strobe signal,
the performing of the fourth duty correction comprises connecting a multiplexer with an output terminal of the buffer chip using a closed state of a fourth switch to control a flow of the data signal, and the operating method further comprises, responsive to the second duty correction, operating the third switch and the fourth switch to the closed states, respectively.

14 . The operating method of claim 9 , further comprising, responsive to selecting at least one non-volatile memory from among the plurality of non-volatile memories, providing data signal duty correction information and data strobe signal duty correction information for the at least one non-volatile memory that was selected.

15 . An interface circuit of a memory system, the interface circuit configured to connect a memory d

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kavala Anil
• Jo Youngmin
• Park Jungjune
• Yoon Chiweon

Classifications

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C7/1078

  Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits · CPC title

• H03K5/1565

  the output pulses having a constant duty cycle · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title