Electronic component placed on core of substrate

Patent metadata

Field	Value
Publication number	US-12581966-B2
Application number	US-202318310388-A
Country	US
Kind code	B2
Filing date	May 1, 2023
Priority date	May 1, 2023
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

In an aspect, a substrate includes a core that includes a core dielectric and a first conductive pattern on a first surface of the core dielectric, and a first metallization structure over the first surface of the core dielectric. The first metallization structure includes a first dielectric, and the first dielectric has a first opening formed therein. The substrate further includes a first electronic component disposed in the first opening of the first dielectric, and a first adhesive layer coupling the first electronic component with the core.

First claim

What is claimed is:

1 . A substrate, comprising:
a core that includes a core dielectric and a first conductive pattern on a first surface of the core dielectric; a first metallization structure over the first surface of the core dielectric, the first metallization structure including a first dielectric, and the first dielectric having a first opening formed therein; a first electronic component disposed in the first opening of the first dielectric; and a first adhesive layer coupling the first electronic component with the core, wherein a space between a sidewall of the first dielectric and a sidewall of the first electronic component is at least partially filled with the first adhesive layer, and the first adhesive layer touches the sidewall of the first dielectric.

2 . The substrate of claim 1 , wherein a thickness of the first electronic component is equal to or less than a thickness of the first dielectric.

3 . The substrate of claim 1 , wherein the first adhesive layer comprises a resin material.

4 . The substrate of claim 3 , wherein the sidewall of the first dielectric is defined by the first opening of the first dielectric.

5 . The substrate of claim 1 , wherein the first adhesive layer includes a bonding film.

6 . The substrate of claim 5 , wherein:
the first metallization structure further includes one other dielectric over the first dielectric, the one other dielectric comprising a dielectric material.

7 . The substrate of claim 1 , wherein:
the core includes a second conductive pattern on a second surface of the core dielectric, and the substrate further comprises:
a second metallization structure under the second surface of the core dielectric, the second metallization structure including a second dielectric, and the second dielectric having a second opening formed therein;
a second electronic component disposed in the second opening of the second dielectric; and
a second adhesive layer coupling the second electronic component with the core.

8 . The substrate of claim 1 , further comprising:
first conductive terminals on an upper surface of the first metallization structure, the first conductive terminals being electrically coupled with at least a portion of the first conductive pattern through the first metallization structure.

9 . The substrate of claim 8 , wherein:
the core includes a second conductive pattern on a second surface of the core dielectric, and the substrate further comprises:
a second metallization structure under the second surface of the core dielectric; and
second conductive terminals on a lower surface of the second metallization structure, the second conductive terminals being electrically coupled with at least a portion of the second conductive pattern through the second metallization structure.

10 . The substrate of claim 1 , wherein the first adhesive layer comprises:
a resin material that includes a polymer resin, an epoxy resin, or a combination thereof, or an adhesive material that is based on the resin material, a non-resin material, or a combination thereof.

11 . The substrate of claim 1 , wherein the core is a copper clad laminate (CCL) core.

12 . A method of manufacturing a substrate, comprising:
forming a first dielectric over a core of the substrate, the core including a core dielectric and a first conductive pattern on a first surface of the core dielectric, the first dielectric being disposed over the first surface of the core dielectric, and the first dielectric being a first portion of a first metallization structure of the substrate over the first surface of the core dielectric; forming a first opening of the first dielectric, the first opening exposing at least a first portion of the core; mounting a first electronic component on the core based on a first adhesive layer coupling the first electronic component with the core, the first electronic component being disposed in the first opening of the first dielectric; and forming a second portion of the first metallization structure over the first dielectric and the first electronic component; wherein a space between a sidewall of the first dielectric and a sidewall of the first electronic component is at least partially filled with the first adhesive layer, and the first adhesive layer touches the sidewall of the first dielectric.

13 . The method of claim 12 , wherein the mounting the first electronic component on the core comprises:
dispensing a resin material, in an uncured form or a partially cured form, in the first opening on at least the first portion of the core; placing the first electronic component in the first opening, wherein the dispensed resin material, in the uncured form or the partially cured form, a portion of a gap between the sidewall of the first dielectric and the sidewall of the first electronic component; and curing the dispensed resin material such that the dispensed resin material, in a cured form, becomes the first adhesive layer.

14 . The method of claim 13 , wherein the curing the dispensed resin material is performed during a build-up curing process for the forming the second portion of the first metallization structure.

15 . The method of claim 13 , wherein the dispensed resin material, in the uncured form or the partially cured form, at least partially fills a space between a sidewall of the first opening and a sidewall of the first electronic component.

16 . The method of claim 12 , wherein the mounting the first electronic component on the core comprises:
placing the first electronic component together with a bonding film in the first opening, the bonding film being used as the first adhesive layer.

17 . The method of claim 12 , further comprising:
forming a second dielectric under the core of the substrate, the core including a second conductive pattern on a second surface of the core dielectric, the second dielectric being disposed under the second surface of the core dielectric, and the second dielectric being a first portion of a second metallization structure of the substrate under the second surface of the core dielectric; forming a second opening of the second dielectric, the second opening exposing at least a second portion of the core; mounting a second electronic component on the core based on a second adhesive layer coupling the second electronic component with the core, the second electronic component being disposed in the second opening of the second dielectric; and forming a second portion of the second metallization structure under the second dielectric and the second electronic component.

18 . The method of claim 12 , further comprising:
forming first conductive terminals on an upper surface of the first metallization structure, the first conductive terminals being electrically coupled with at least a portion of the first conductive pattern through the first metallization structure.

19 . The method of claim 18 , further comprising:
forming a second metallization structure under the core of the substrate, the core including a second conductive pattern on a second surface of the core dielectric, and the second metallization structure being disposed under the second surface of the core dielectric; and forming second conductive terminals on a lower surface of the second metallization structure, the second conductive terminals being electrically coupled with at least a portion of the second conductive pattern through the second metallization structure.

20 . The method of claim 12 ,

Assignees

• Qualcomm Inc

Inventors

• We Hong Bok
• Buot Joan Rey Villarba
• Kim Michelle Yejin
• Kang Kuiwon

Classifications

• H10W72/30

  Die-attach connectors · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07337

  using a polymer adhesive, e.g. an adhesive based on silicone or epoxy · CPC title

• H10W72/354

  comprising polymers · CPC title