Microwave integrated circuits including gallium-nitride devices on silicon

Patent metadata

Field	Value
Publication number	US-12581728-B2
Application number	US-202318170794-A
Country	US
Kind code	B2
Filing date	Feb 17, 2023
Priority date	Mar 26, 2020
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

Various methods of forming integrated circuits formed using gallium nitride and other materials are described. An example method includes forming a first integrated device over a first semiconductor structure in a first region of the integrated circuit, forming a second integrated device over a second semiconductor structure in a second region of the integrated circuit, etching a cavity in a third region of the of the integrated circuit located between the first region and the second region, filling the cavity with an insulating material, and forming a passive component over the insulating material in the third region of the integrated circuit. In other aspects, the method can include grinding a back side of a semiconductor substrate of the integrated circuit to electrically isolate the first semiconductor structure from the second semiconductor structure and, after the grinding, forming a ground plane over the back side of the semiconductor substrate.

First claim

The invention claimed is:

1 . A method of forming an integrated circuit, the method comprising:
forming a first integrated device over a first semiconductor structure in a first region of the integrated circuit; forming a second integrated device over a second semiconductor structure in a second region of the integrated circuit; etching a cavity in a third region of the of the integrated circuit located between the first region and the second region; filling the cavity with an insulating material; forming a passive component over the insulating material in the third region of the integrated circuit; and grinding a back side of a semiconductor substrate of the integrated circuit to electrically isolate the first semiconductor structure from the second semiconductor structure.

2 . A method of forming an integrated circuit, comprising:
forming a first integrated device over a first semiconductor structure in a first region of the integrated circuit; forming a second integrated device over a second semiconductor structure in a second region of the integrated circuit; etching a cavity in a third region of the of the integrated circuit located between the first region and the second region; filling the cavity with an insulating material; and forming a passive component over the insulating material in the third region of the integrated circuit, wherein:
the passive component comprises a network of passive components; and
the network of passive components comprises at least one capacitor and at least one inductor.

3 . The method of claim 1 , wherein:
the first semiconductor structure comprises an island of gallium nitride material formed over a semiconductor substrate; and the first integrated device is formed in the island of gallium nitride material.

4 . The method of claim 3 , wherein, in the third region, the insulating material extends down into the semiconductor substrate to at least a distance below an interface between the island of gallium nitride material and the semiconductor substrate in the first region.

5 . The method of claim 1 , wherein the insulating material comprises glass.

6 . The method of claim 1 , wherein:
the first semiconductor structure comprises a first island of gallium nitride material formed over a semiconductor substrate; the first integrated device is formed in the first island of gallium nitride material; the second semiconductor structure comprises a second island of gallium nitride material formed over the semiconductor substrate; and the second integrated device is formed in the second island of gallium nitride material.

7 . The method of claim 1 , further comprising encapsulating the integrated circuit with a passivation layer.

8 . The method of claim 1 , further comprising depositing a conductive film over a back side of a semiconductor substrate of the integrated circuit.

9 . The method of claim 1 , further comprising, after the grinding, forming a ground plane over the back side of the semiconductor substrate.

10 . The method of claim 9 , wherein, after forming the ground plane, the insulating material contacts the ground plane in the third region between the first semiconductor structure and the second semiconductor structure.

11 . The method of claim 1 , further comprising forming a layer of gallium nitride material over a semiconductor substrate of the integrated circuit before the etching.

12 . The method of claim 11 , further comprising depositing a conductive film over the first semiconductor structure, the second semiconductor structure, and the cavity after forming the layer of gallium nitride material and after the etching.

13 . A method of forming an integrated circuit, comprising:
forming a first integrated device over a first semiconductor structure in a first region of the integrated circuit; forming a second integrated device over a second semiconductor structure in a second region of the integrated circuit; etching a cavity in a third region of the of the integrated circuit located between the first region and the second region; filling the cavity with an insulating material; and forming a passive component over the insulating material in the third region of the integrated circuit, wherein, after the etching, the integrated circuit comprises a semiconductor pedestal in the third region.

14 . The method of claim 13 , further comprising depositing a conductive film over the semiconductor pedestal after the etching.

15 . The method of claim 14 , further comprising:
grinding a back side of a semiconductor substrate of the integrated circuit to electrically isolate the first semiconductor structure from the second semiconductor structure after depositing the conductive film; and after the grinding, forming a ground plane over the back side of the semiconductor substrate.

16 . The method of claim 15 , wherein the conductive film over the semiconductor pedestal is electrically coupled to the ground plane.

17 . A method of forming an integrated circuit, the method comprising:
forming a layer of gallium nitride material over a semiconductor substrate of the integrated circuit; etching a cavity in a third region of the of the integrated circuit located between a first region and a second region of the integrated circuit; filling the cavity with an insulating material; forming a first integrated device over a first semiconductor structure in the first region of the integrated circuit; forming a second integrated device over a second semiconductor structure in the second region of the integrated circuit; grinding a back side of a semiconductor substrate of the integrated circuit to electrically isolate the first semiconductor structure from the second semiconductor structure; and forming a ground plane over the back side of the semiconductor substrate.

18 . The method of claim 17 , wherein, after forming the ground plane, the insulating material contacts the ground plane in the third region between the first semiconductor structure and the second semiconductor structure.

19 . The method of claim 17 , wherein after the etching, the integrated circuit comprises a semiconductor pedestal in the third region, and the method further comprises:
depositing a conductive film over the semiconductor pedestal; grinding a back side of a semiconductor substrate of the integrated circuit to electrically isolate the first semiconductor structure from the second semiconductor structure; and after the grinding, forming a ground plane over the back side of the semiconductor substrate.

20 . The method of claim 19 , wherein the conductive film over the semiconductor pedestal is electrically coupled to the ground plane.

Assignees

• Macom Tech Solutions Holdings Inc

Inventors

• Carlson Douglas
• Boles Timothy E
• Struble Wayne Mack

Classifications

• H10W44/251

  for monolithic microwave integrated circuits [MMIC] · CPC title

• H10W44/241

  for passive devices or passive elements · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title