Switching slew rate control of cascode switch device and gate driver thereof

Patent metadata

Field	Value
Publication number	US-12580561-B2
Application number	US-202318543088-A
Country	US
Kind code	B2
Filing date	Dec 18, 2023
Priority date	Dec 18, 2023
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

A cascode switch device includes a normally-on switch device, a normally-off switch device, and a gate driver. The normally-on switch device has a first terminal, a second terminal and a control terminal. The normally-off switch device has a first terminal, a second terminal and a control terminal. The first terminal of the normally-off switch device is coupled to the second terminal of the normally-on switch device, and the control terminal of the normally-off switch device is coupled to the control terminal of the normally-on switch device. The gate driver is configured to provide a gate driver signal to the control terminal of the normally-on switch device to control a switching slew rate of a voltage at the first terminal of the normally-on switch device. The normally-on switch device is turned on or turned off in response to the gate driver signal.

First claim

What is claimed is:

1 . A cascode switch device, comprising:
a normally-on switch device having a first terminal, a second terminal and a control terminal; a normally-off switch device having a first terminal, a second terminal and a control terminal, wherein the first terminal of the normally-off switch device is coupled to the second terminal of the normally-on switch device, and the control terminal of the normally-off switch device is coupled to the control terminal of the normally-on switch device; and a gate driver configured to provide a gate driver signal to the control terminal of the normally-on switch device to control a switching slew rate of a voltage at the first terminal of the normally-on switch device; wherein the gate driver comprises:
a first driver configured to provide a driver signal with a first driving capability to the control terminal of the normally-off switch device; and
a second driver configured to provide a driver signal with a second driving capability different from the first driving capability to the control terminal of the normally-off switch device; and
wherein the normally-on switch device is turned on or turned off in response to the gate driver signal.

2 . The cascode switch device of claim 1 , wherein the gate driver comprises:
a current limiting circuit configured to provide a limited current flowing to the control terminal of the normally-on switch device.

3 . The cascode switch device of claim 1 , wherein the gate driver comprises:
a voltage drop circuit coupled between the control terminal of the normally-on switch device and the control terminal of the normally-off switch device, wherein the voltage drop circuit is configured to provide the gate driver signal to the control terminal of the normally-on switch device, and a voltage of the gate driver signal is lower than a voltage of the driver signal.

4 . The cascode switch device of claim 3 , wherein the voltage drop circuit comprises a switch, and the gate driver further comprises:
a timing circuit configured to provide a control signal to turn on the switch when the normally-off switch device is turned on in response to the driver signal.

5 . The cascode switch device of claim 4 , wherein the timing circuit is further configured to provide the control signal to turn off the switch a time period after the normally-off switch device is turned on.

6 . The cascode switch device of claim 4 , wherein the gate driver further comprises:
a current limiting circuit configured to provide a limited current flowing to the control terminal of the normally-on switch device after the time period.

7 . The cascode switch device of claim 1 , wherein the normally-on switch device includes a wide-bandgap (WBG) semiconductor switch, and the WBG semiconductor switch is integrated on a first die, and the gate driver and the normally-off switch device are integrated on a second die.

8 . A power switch device, comprising:
a first transistor having a first source, a first drain and a first gate; and a second transistor having a second source, a second drain and a second gate; a gate driver configured to provide a gate driver signal to the first gate of the first transistor to control a switching slew rate of a voltage at the first drain of the first transistor; wherein the gate driver comprises:
a first driver configured to provide a driver signal with a first driving capability to the control terminal of the second transistor; and
a second driver configured to provide a driver signal with a second driving capability different from the first driving capability to the control terminal of the second transistor;
wherein the first transistor is turned on or turned off in response to the gate driver signal.

9 . The power switch device of claim 8 , wherein the gate driver comprises:
a current source configured to provide a limited current flowing to the first gate of the first transistor.

10 . The power switch device of claim 8 , wherein the gate driver comprises:
a third transistor coupled between the first gate of the first transistor and the second gate of the second transistor, wherein the third transistor is configured to be turned on to provide the gate driver signal to the first gate of the first transistor, and a voltage of the gate driver signal is lower than a voltage of the driver signal.

11 . The power switch device of claim 10 , wherein the gate driver further comprises:
a timing circuit configured to provide a control signal to turn on the third transistor when the second transistor is turned on in response to the driver signal.

12 . The power switch device of claim 11 , wherein the timing circuit is further configured to provide the control signal to turn off the third transistor a time period after the second transistor is turned on.

13 . The power switch device of claim 11 , wherein the gate driver further comprises:
a current source configured to provide a limited current flowing to the first gate of the first transistor after the time period.

14 . The power switch device of claim 11 , wherein the first transistor includes a Junction Field-Effect Transistor (JFET), and the second transistor includes a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET).

15 . The power switch device of claim 11 , wherein the first transistor includes is integrated on a WBG die, and the gate driver and the second transistor are integrated on a second die.

16 . A gate driver for driving a cascode switch device having a normally-on switch device and a normally-off switch device, wherein the gate driver comprises:
a driver circuit configured to provide a gate driver signal to a control terminal of the normally-on switch device and a control terminal of the normally-off switch device to control a switching slew rate of a voltage at a first terminal of the normally-on switch device; wherein the driver circuit comprises:
a first driver configured to provide a driver signal with a first driving capability to the control terminal of the normally-off switch device; and
a second driver configured to provide a driver signal with a second driving capability different from the first driving capability to the control terminal of the normally-off switch device;
wherein the normally-on switch device is turned on or turned off in response to the gate driver signal.

17 . The gate driver of claim 16 , further comprising:
a current limiting circuit configured to provide a limited current flowing to the control terminal of the normally-on switch device.

18 . The gate driver of claim 16 , further comprising:
a voltage drop circuit coupled between the control terminal of the normally-on switch device and the control terminal of the normally-off switch device, wherein the voltage drop circuit is configured to receive and driver signal and provide the gate driver signal to the control terminal of the normally-on switch device, and a voltage of the gate driver signal is lower than a voltage of the driver signal.

19 . The gate driver of claim 18 , wherein the voltage drop circuit comprises a switch, and the gate driver further comprises:
a timing circuit configured to provide a control signal to turn on the switch when the normally-off switch device is turned on in response to the driver signal.

20 . The gate driver of claim 19 , wherein the timing circuit is further configured to provide the control signal to turn off the switch a time period after the normally-off switch device is turn

Assignees

• Monolithic Power Systems Inc

Inventors

• Pala Vipindas
• Cheng Xiao-Chang
• Han Di

Classifications

• H03K17/08122

  in field-effect transistor switches · CPC title

• H03K2217/94047

  Cascode connected switches · CPC title

• H03K2017/066

  Maximizing the OFF-resistance instead of minimizing the ON-resistance · CPC title

• H03K17/102

  in field-effect transistor switches · CPC title

• H03K17/04123

  in field-effect transistor switches · CPC title