Circuit with transistors having coupled gates

Patent metadata

Field	Value
Publication number	US-10218350-B2
Application number	US-201615215310-A
Country	US
Kind code	B2
Filing date	Jul 20, 2016
Priority date	Jul 20, 2016
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

A circuit can include a first transistor including a source and a gate; a second transistor including a drain and a gate, wherein the source of the first transistor is coupled to the drain of the second transistor; and a switchable element. In one embodiment, a first current-carrying terminal of the switchable element is coupled to the gate of the first transistor, and a second current-carrying terminal of the switchable element is coupled to the gate of the second transistor. In another embodiment, the switchable element is coupled to the gate of the first transistor and includes a first selectable terminal of the switchable element coupled to a source of the second transistor, and a second selectable terminal of the switchable element coupled to the gate of the second transistor. In a particular embodiment, the circuit can be a cascode circuit.

First claim

What is claimed is:

1. A circuit comprising:
a first transistor including a source and a gate, wherein the first transistor is a HEMT;
a second transistor including a drain and a gate, wherein the source of the first transistor is coupled to the drain of the second transistor; and
a switchable element including a first current-carrying terminal and a second current carrying terminal, wherein the first current-carrying terminal of the switchable element is coupled to the gate of the first transistor, and the second current-carrying terminal of the switchable element is coupled to the gate of the second transistor.

2. The circuit of claim 1 , wherein the switchable element includes a third transistor that is a field-effect transistor.

3. The circuit of claim 2 , wherein the third transistor is a depletion-mode transistor.

4. The circuit of claim 2 , wherein the third transistor is a MISFET.

5. The circuit of claim 2 , wherein the first current-carrying terminal of the switchable element is a drain of the third transistor, and the second current-carrying terminal of the switchable element is a source of the third transistor.

6. The circuit of claim 2 , wherein the third transistor further includes a gate coupled to the source of the first transistor and the drain of the second transistor.

7. The circuit of claim 2 , wherein the third transistor further includes a gate coupled to a switch controller outside the circuit.

8. The circuit of claim 2 , wherein the first transistor is a depletion-mode transistor, and the second transistor is an enhancement-mode transistor.

9. The circuit of claim 1 , further comprising a first passive component coupled between the second current-carrying terminal of the switchable element and a control terminal of the circuit or the gate of the second transistor.

10. The circuit of claim 9 , further comprising a second passive component, wherein:
the first passive component is coupled between the second current-carrying terminal of the switchable element and the control terminal of the circuit; and
the second passive component is coupled between the second current-carrying terminal of the switchable element and the gate of the second transistor.

11. The circuit of claim 10 , wherein the first passive component is a first resistor having a first resistance, the second passive component is a second resistor having a second resistance that is greater than the first resistance.

12. The circuit of claim 10 , wherein a substrate of the first transistor is coupled to the source of the second transistor.

13. The circuit of claim 1 , wherein a control terminal of the circuit, the gate of the second transistor, and the second current-carrying terminal of the switchable element are electrically connected at a node.

14. The circuit of claim 13 , wherein the gate of the first transistor is not electrically connected to the node.

15. The circuit of claim 1 , wherein the first transistor is a depletion-mode transistor, and the second transistor is an enhancement-mode Si MISFET.

16. The circuit of claim 1 , wherein:
the gate of the first transistor and the first current-carrying terminal of the switchable element are electrically connected at a first node,
a control terminal of the circuit, the gate of the second transistor, and the second current-carrying electrode of the switchable element are electrically connected at a second node.

17. A circuit comprising:
a first transistor including a source and a gate;
a second transistor including a drain and a gate, wherein the source of the first transistor is coupled to the drain of the second transistor; and
a switchable element including a gate, a first current-carrying terminal and a second current carrying terminal, wherein:
the first current-carrying terminal of the switchable element is coupled to the gate of the first transistor,
the second current-carrying terminal of the switchable element is coupled to the gate of the second transistor, and
the switchable element includes a third transistor that is a field-effect transistor, wherein a gate of the third transistor is coupled to the source of the second transistor.

18. The circuit comprising:
a first transistor including a source and a gate, wherein the first transistor is a depletion-mode GaN HEMT;
a second transistor including a drain and a gate, wherein the second transistor is an enhancement-mode Si MISFET, and the source of the first transistor is coupled to the drain of the second transistor; and
a switchable element including a first current-carrying terminal and a second current carrying terminal, wherein the switchable element is a depletion-mode Si MISFET or GaN HEMT, the first current-carrying terminal of the switchable element is coupled to the gate of the first transistor, and the second current-carrying terminal of the switchable element is coupled to the gate of the second transistor.

19. The circuit of claim 18 , wherein a gate of the third transistor is electrically connected to the source of the second transistor.

20. The circuit of claim 18 , wherein a gate of the third transistor is electrically connected to the source of the first transistor and the drain of the second transistor.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Roig-Guitart Jaume
• Padmanabhan Balaji
• Venkatraman Prasad

Classifications

• H03K2217/0036

  Means reducing energy consumption · CPC title

• H03K2217/0054

  Gating switches, e.g. pass gates · CPC title

• H03K17/165 Primary

  by feedback from the output circuit to the control circuit · CPC title