Apparatus and method of damage mitigation and step coverage enhancement

Patent metadata

Field	Value
Publication number	US-12580152-B2
Application number	US-202418926504-A
Country	US
Kind code	B2
Filing date	Oct 25, 2024
Priority date	Nov 10, 2023
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

Embodiments described herein provide an apparatus and method for fabricating semiconductor devices with improved process control and performance. The apparatus includes a processing chamber with first and second RF coil assemblies generating primary and secondary plasmas in distinct regions, along with first and second electromagnet assemblies for independent magnetic field control. A removable biasable flux optimizer is disposed in the apparatus to modulate plasma distribution and directionality. The method involves a three-step sequence comprising Inductive coupled plasma (IMP) low energy deposition, deposition for enhanced step coverage, and etching for overhang removal. The ICP deposition utilizes primary and secondary plasmas generated by the RF coil assemblies, with intensified collisions achieved through chamber pressure increase. Additionally, a simultaneous deposition and etching process can be employed, with optional additional etching steps for improved overhang removal.

First claim

What is claimed is:

1 . A method for fabricating a semiconductor device, comprising:
forming, within a process chamber, a first layer on a surface of a substrate that comprises a plurality of features formed therein, wherein forming the first layer comprises:
biasing a target at a first target bias power;
biasing an inductive coil at a first RF bias power while the target is biased to the first target bias power, wherein the inductive coil is disposed between the target and a substrate support that is configured to support the substrate;
applying a first voltage bias to a collimator disposed between the target and the inductive coil; and
adjusting a pressure within a processing region of the process chamber to a first process pressure;
forming, within the process chamber, a second layer on the surface of the substrate, wherein forming the second layer comprises:
biasing the target at a second target bias power, wherein the second target bias power is greater than the first target bias power;
biasing the inductive coil at a second RF bias power, wherein the second RF bias power is less than the first RF bias power;
applying a second voltage bias to the collimator, wherein the first voltage bias is less than the second voltage bias; and
adjusting the pressure within the processing region of the process chamber to a second process pressure, wherein the second process pressure is less than the first process pressure; and
exposing, within the process chamber, at least a portion of the second layer to a plasma containing an inert gas, wherein exposing the at least a portion of the second layer comprises:
biasing the inductive coil at a third RF bias power, wherein the third RF bias power is greater than the second RF bias power; and
adjusting the pressure within the processing region of the process chamber to a third process pressure, wherein the third process pressure is less than the first process pressure.

2 . The method of claim 1 , wherein the second RF bias power is equal to zero.

3 . The method of claim 1 , wherein the first layer has a thickness that is between 10 angstroms (Å) and 100 Å.

4 . The method of claim 1 , wherein the second layer has a thickness that is between 100 angstroms (Å) and 1000 Å.

5 . The method of claim 1 , wherein
the forming the first layer on the surface of the substrate further comprises:
applying a first substrate bias to an electrode disposed within the substrate support;
the forming the second layer on the surface of the substrate further comprises:
applying a second substrate bias to the electrode disposed within the substrate support, wherein the second substrate bias is greater than the first substrate bias; and
the exposing the at least a portion of the second layer to the plasma further comprises:
applying a third substrate bias to the electrode disposed within the substrate support, wherein the third substrate bias is greater than the second substrate bias.

6 . The method of claim 1 , wherein the inductive coil and the target comprise the same material.

7 . The method of claim 6 , wherein the inductive coil is disposed within the process region.

8 . A method for fabricating a semiconductor device, comprising:
forming, within a process chamber, a first layer on a surface of a substrate that comprises a plurality of features formed therein, wherein forming the first layer comprises:
biasing a target at a first target bias power;
biasing an inductive coil at a first RF bias power while the target is biased to the first target bias power, wherein the inductive coil is disposed between the target and a substrate support that is configured to support the substrate;
applying a first voltage bias to a collimator disposed between the target and the inductive coil;
adjusting a pressure within a processing region of the process chamber to a first process pressure; and
generating a first magnetic field within the process region by biasing a first external coil; and
forming, within the process chamber, a second layer on the surface of the substrate, wherein forming the second layer comprises:
biasing the target at a second target bias power, wherein the second target bias power is greater than the first target bias power;
biasing the inductive coil at a second RF bias power, wherein the second RF bias power is less than the first RF bias power;
applying a second voltage bias to the collimator, wherein the first voltage bias is less than the second voltage bias;
adjusting the pressure within the processing region of the process chamber to a second process pressure, wherein the second process pressure is less than the first process pressure;
generating a second magnetic field within the process region by biasing the first external coil; and
applying a first substrate bias to an electrode disposed within the substrate support.

9 . The method of claim 8 , wherein the second RF bias power is equal to zero.

10 . The method of claim 8 , wherein the first layer has a thickness that is between 10 angstroms (Å) and 100 Å.

11 . The method of claim 8 , wherein the second layer has a thickness that is between 100 angstroms (Å) and 1000 Å.

12 . The method of claim 8 , wherein
the forming the first layer on the surface of substrate further comprises:
applying a substrate bias to the electrode disposed within the substrate support.

13 . The method of claim 8 , wherein the inductive coil and the target comprise a same material.

14 . The method of claim 13 , wherein the inductive coil is disposed within the process region.

Assignees

• Applied Materials Inc

Inventors

• Mebarki Bencherki
• Kim Sang-Heum
• Lee Joung Joo

Classifications

• C23C14/3492

  Variation of parameters during sputtering · CPC title

• H01J37/3266

  Magnetic control means · CPC title

• C23C14/345

  using substrate bias · CPC title

• C23C14/358

  Inductive energy · CPC title

• H01J2237/332

  Coating · CPC title