Read-only memory method, layout, and device

Patent metadata

Field	Value
Publication number	US-12580033-B2
Application number	US-202318346736-A
Country	US
Kind code	B2
Filing date	Jul 3, 2023
Priority date	Jul 3, 2023
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

A method of generating an IC layout diagram includes dividing a column of NOR-type read-only memory (ROM) bit cells into a plurality of N-bit groups separated by isolation features, wherein each group includes the number of bits N greater than two, based on a ROM code programming pattern of the column, assigning one or more logic patterns to each N-bit group of the plurality of N-bit groups, and storing an IC layout diagram including the logic patterns in a storage device.

First claim

What is claimed is:

1 . A method of generating an integrated circuit (IC) layout diagram, the method comprising:
dividing a column of NOR-type read-only memory (ROM) bit cells into a plurality of N-bit groups separated by isolation features, wherein each group includes the number of bits N greater than two; based on a ROM code programming pattern of the column, assigning one or more logic patterns to each N-bit group of the plurality of N-bit groups; and storing an IC layout diagram including the logic patterns in a storage device.

2 . The method of claim 1 , wherein the assigning the one or more logic patterns to each N-bit group of the plurality of N-bit groups comprises assigning a single N-bit logic pattern to each N-bit group of the plurality of N-bit groups.

3 . The method of claim 2 , wherein
the number of bits N is equal to four, and each logic pattern comprises at least two via regions overlapping a power supply line or a bit line and a source/drain (S/D) region of a ROM bit cell transistor.

4 . The method of claim 1 , further comprising:
dividing each N-bit group into a plurality of M-bit units, wherein
the number of bits N is a multiple of the number of bits M, and
the assigning the one or more logic patterns to each N-bit group of the plurality of N-bit groups comprises assigning one or more logic patterns to each M-bit unit of the plurality of M-bit units of each N-bit group of the plurality of N-bit groups.

5 . The method of claim 4 , wherein
the assigning each logic pattern of the one or more logic patterns to each M-bit unit of the plurality of M-bit units of each N-bit group of the plurality of N-bit groups comprises assigning the logic pattern comprising upper and lower boundary electrical connections capable of being included in each of a 0-bit ROM cell configuration and a 1-bit ROM cell configuration.

6 . The method of claim 5 , wherein
the column of NOR-type ROM bit cells comprises a power supply line and a bit line, each ROM bit cell comprises a transistor comprising a gate coupled to a word line, and the assigning the logic pattern comprising the upper and lower boundary electrical connections comprises arranging IC layout features at each boundary to establish one of
a first connection type comprising an electrical connection between a first source/drain (S/D) region of the transistor and the power supply line, or
a second connection type comprising an electrical connection between the first S/D region of the transistor and the bit line.

7 . The method of claim 6 , wherein the assigning the one or more logic patterns to each M-bit unit of the plurality of M-bit units of an N-bit group of the plurality of N-bit groups further comprises:
assigning a first logic pattern to a first M-bit unit of the plurality of M-bit units at a first end of the N-bit group; and sequentially assigning additional logic patterns to successive adjacent M-bit units of the plurality of M-bit units, wherein the corresponding logic patterns of adjacent M-bit units of the plurality of M-bit units comprise shared upper and lower boundaries comprising the first or second connection type.

8 . The method of claim 6 , wherein
the 0-bit ROM cell configuration comprises:
the first connection type and another electrical connection between a second S/D region of the transistor and the power supply line,
the second connection type and another electrical connection between the second S/D region of the transistor and the bit line, or
one of the first or second connection types and the second S/D region of the transistor electrically isolated from each of the power supply and bit lines, and
the 1-bit ROM cell configuration comprises:
the first connection type and another electrical connection between the second S/D region of the transistor and the bit line, or
the second connection type and another electrical connection between the second S/D region of the transistor and the power supply line.

9 . The method of claim 6 , wherein the arranging the IC layout features at each boundary to establish each of the first and second connection types comprises overlapping a via region with each of the first S/D region of the transistor and the corresponding power supply line or bit line.

10 . The method of claim 1 , further comprising:
generating the one or more logic patterns; and storing the one or more logic patterns in the storage device, wherein the assigning the one or more logic patterns to each N-bit group of the plurality of N-bit groups comprises retrieving the one or more logic patterns from the storage device.

11 . A read-only memory (ROM) integrated circuit (IC) comprising:
a column of NOR-type ROM bit cells aligned in a column direction, wherein each ROM bit cell comprises a fin field-effect transistor (FinFET) comprising:
a gate structure extending perpendicular to the column direction; and
source/drain (S/D) structures adjacent to the gate structure;
a power supply line and a bit line, each extending in the column direction and overlying each gate structure and S/D structure of the column of ROM bit cells; and a plurality of isolation structures configured to divide the column of ROM bit cells into electrically isolated groups of ROM bit cells, wherein
each pair of adjacent ROM bit cells within each group of ROM bit cells shares a corresponding S/D structure, and
each group of ROM bit cells of the column of ROM bit cells comprises a total number of ROM bit cells greater than two.

12 . The ROM IC of claim 11 , wherein
the total number of ROM bit cells of each group of ROM bit cells of the column of ROM bit cells is equal to four, and each group of ROM bit cells comprises at least two via structures configured to electrically connect the power supply line or the bit line to an underlying S/D structure of a ROM bit cell transistor.

13 . The ROM IC of claim 11 , wherein
each group of ROM bit cells of the column of ROM bit cells comprises a plurality of units of ROM bit cells, the total number of ROM bit cells of each group of ROM bit cells is a multiple of a total number of ROM bit cells of each unit of each plurality of units of ROM bit cells, and each location corresponding to adjacent units of each plurality of units of ROM bit cells comprises a via structure configured to electrically connect the power supply line or the bit line to the corresponding underlying shared S/D structure.

14 . The ROM IC of claim 11 , wherein each ROM bit cell of the column of ROM bit cells comprises a via structure configured to electrically connect the power supply line or the bit line to an underlying S/D structure of the corresponding ROM bit cell transistor.

15 . A method of manufacturing a read-only memory (ROM) integrated circuit (IC), the method comprising:
forming a column of NOR-type ROM bit cells aligned in a column direction, wherein the forming each ROM bit cell comprises forming a fin field-effect transistor (FinFET) by:
constructing a gate structure extending perpendicular to the column direction; and
forming source/drain (S/D) structures adjacent to the gate structure;
forming a plurality of isolation structures configured to divide the column of ROM bit cells into electrically isolated groups of ROM bit cells; and constructing a power supply line and a bit line, each extending in the column direction and overlying each gate structure and S/D structure of the column of ROM bit cells, wherein
each pair of adjacent ROM bit cells within each group of ROM bit cells shares a corresponding S/D structure, and
each group of ROM bit cells of t

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Ku-Feng
• Huang Chia-En
• Lee Chieh
• Uno Kazumasa
• Wu Ching-Wei

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• H10B20/20

  Programmable ROM [PROM] devices comprising field-effect components (H10B20/10 takes precedence) · CPC title

• H10B20/40

  having the source region and drain region on different levels, e.g. vertical channel · CPC title