Programmability of a field-programmable gate array via a dual-mode port

Patent metadata

Field	Value
Publication number	US-12579352-B2
Application number	US-202217953317-A
Country	US
Kind code	B2
Filing date	Sep 26, 2022
Priority date	Jul 24, 2020
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

A programmable semiconductor system includes a programmable integrated circuit (“PIC”) and storage capable of facilitating a multi-boot with backup default configuration (“MBC”) process. The PIC, in one embodiment, includes a dual-mode port (“DMP”), configurable logic blocks (“LBs”), routing connections, and a configuration memory for providing configuration data to facilitate user-defined logic functions. The DMP, in one aspect, is operable to handle the configuration data during a configuration mode. Alternatively, the DMP is operable to handle the user data during a logic operation mode. In one aspect, the user configuration data contains the address of the second memory containing DCD.

First claim

What is claimed is:

1 . A programmable device having a configurable pin to switch between configuration mode and logic operation mode for data transmission, the device comprising:
a storage organized in multiple addressable memory regions wherein each memory region stores at least a version of configuration data and a memory address for addressing next memory region utilized for storing another version of configuration data; a configurable port of a field-programmable gate array (“FPGA”), coupled to the storage, capable of being switched to a configuration mode when a stream of configuration data for programming configurable logic blocks of FPGA is transmitted; and a pin controller coupled to the configurable port and capable of maintaining the configurable port operational when current version of configuration data in FPGA is defective whereby a new version of configuration data is downloaded from the storage facilitated by the pin controller via the configurable port for replacing the current version of configuration data.

2 . The device of claim 1 , wherein the configurable port is further capable of being switched to a logic operation mode when a stream of user data generated by the configurable logic blocks of the FPGA is transmitted.

3 . The device of claim 1 , where the storage is a nonvolatile memory coupling to the FPGA.

4 . The device of claim 1 , wherein the configurable port is a dual-mode port (“DMP”) for facilitating a multi-boot operation for the FPGA.

5 . The device of claim 1 , wherein the pin controller is a circuit module for facilitating a multi-boot operation for the FPGA.

6 . The device of claim 1 , wherein the pin controller is implemented by FPGA controller for facilitating a multi-boot operation for the FPGA.

7 . The device of claim 1 , wherein the storage stores at least one version of configuration data provided by a user to perform user-defined logic functions.

8 . The device of claim 1 , further comprising a bus coupled to the storage and configured to transmit information.

9 . The device of claim 1 , wherein the FPGA includes a dual-mode port (“DMP”), the configurable logic blocks (“LBs”), routing connections, and a configuration memory for providing configuration data to facilitate user-defined logic functions, each of the configurable LBs including one or more lookup tables (“LUTs”) configured to provide one or more output signals in accordance with a set of input signals and the configuration data.

10 . The device of claim 1 , wherein the configurable port is configured to switch to the configuration mode when the DMP is operable to load the configuration data from the storage to a configuration memory of the FPGA via the bus.

11 . The device of claim 10 , wherein the configurable port is configured to switch to the logic operation mode when the DMP is operable to handle user data after at least a portion of the FPGA is configured.

12 . The device of claim 1 , wherein the storage includes a first memory section configured to store at least a first user configuration data for supplying at least a portion of the configuration data to FPGA.

13 . The device of claim 12 , wherein the storage includes a second memory second configured to store a backup default page (“BDP”) containing default configuration data (“DCD”) from FPGA manufacture for rebooting the FPGA to a manufacturing setting when current configuration data in the FPGA is defective.

14 . The device of claim 13 , wherein the DCD includes pin managing information for control the configurable port to switch between operating modes for transmitting one of the configuration data and the user data.

15 . The device of claim 1 , wherein a user configuration data in a configuration memory includes information to facilitate controlling of the configurable port to switch between modes for transmitting one of configuration data and the user data.

16 . A system able to provide various digital processing functions and network communications comprising the device of claim 1 .

17 . A programmable device having a configurable pin to switch between configuration mode and logic operation mode for data transmission, the device comprising:
a storage organized in multiple addressable memory locations wherein each memory location stores a version of configuration data and a storage address for addressing next memory location which stores another version of configuration data; a dual-mode port (“DMP”) of a field-programmable gate array (“FPGA”), coupled to the storage, capable of being switched to a logic operation mode when a stream of user data generated by the FPGA is transmitted; and a pin switch coupled to the DMP and capable of maintaining operation of the DMP when current version of configuration data in the FPGA is defective so that a new version of configuration data is downloaded from the storage facilitated by the pin switch via the DMP for replacing the current version of configuration data.

18 . The device of claim 17 , wherein the DMP is further capable to being configured to a configuration mode when a stream of configuration data for programming at least a part of FPGA is transmitted.

19 . The device of claim 17 , where the storage is a nonvolatile memory coupling to FPGA.

20 . A method of facilitating a multi-boot process to a field-programmable gate array (“FPGA”) via a configurable pin, the method comprising:
receiving a first data stream of first configuration data from a storage via a configurable dual-mode port (“DMP”) operating in a configuration mode;
activating a verification process to verifying the first configuration data and switching the configurable DMP to a logic operation mode;
detecting one or more defects associated to the first configuration data in accordance with the verification process;
maintaining continuous operation of the configurable DMP despite detecting the defects from the first configuration data;
setting the configurable DMP to the configuration mode from the logic operation in response to the defects; and
loading a second data stream of second configuration data from the storage via the configuration DMP.

21 . The method of claim 20 , further comprising activating the verification process to verifying the second configuration data and switching the configurable DMP from the configuration mode to a logic operation mode.

22 . The method of claim 20 , further comprising extracting an address of a storage location containing the second data bitstream from the first data bitstream when the first configuration data is defective.

23 . The method of claim 20 , further comprising identifying an address of a backup default page (“BDP”) containing default configuration data (“DCD”) capable of rebooting the FPGA to a manufacturing default setting.

24 . The method of claim 20 , further comprising:
generating a second bitstream representing a second set of configuration data by a plurality of configured logic blocks (“LBs”) in the FPGA; and forwarding the second bitstream to the external storage via the configurable DMP.

25 . The method of claim 20 , further comprising:
generating a data stream representing user data updating by a plurality of configured logic blocks (“LBs”) in the FPGA; and sending the data stream to the external storage for storing the user data via the configurable DMP.

Assignees

• Gowin Semiconductor Corp Ltd
• Gowin Semiconductor Corp

Inventors

• Zhu Jinghui
• Chopperla Diwakar

Classifications

• G06F30/347 Primary

  Physical level, e.g. placement or routing · CPC title

• H03K19/17728 Primary

  Reconfigurable logic blocks, e.g. lookup tables · CPC title