Method and apparatus for automatic expansion of storage array, device and medium

Patent metadata

Field	Value
Publication number	US-12579349-B2
Application number	US-202217954468-A
Country	US
Kind code	B2
Filing date	Sep 28, 2022
Priority date	Dec 21, 2021
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

A method for automatic expansion of a storage array includes: acquiring a word-line total number and bit-line total number of a target expanded storage array; calculating a translation amount of a translation array in a translation direction according to the word-line total number and the bit-line total number, a word-line total number and bit-line total number of the translation array and a preset translation rule, and calculating a number of repetitions of a repetition array in a repetition direction according to the translation amount, a word-line total number and bit-line total number of the repetition array and a preset repetition rule; and controlling at least part of the translation array and at least part of the repetition array to translate the translation amount along the translation direction and controlling the repetition array to repeat for the number of repetitions along the repetition direction to obtain the target expanded storage array.

First claim

The invention claimed is:

1 . A method for automatic expansion of a storage array, comprising:
acquiring a total number of word lines of a target expanded storage array and a total number of bit lines of the target expanded storage array; calculating a translation amount of a translation array in a translation direction according to the total number of word lines, the total number of bit lines, a total number of word lines of the translation array, a total number of bit lines of the translation array, and a preset translation rule, and calculating a number of repetitions of a repetition array in a repetition direction according to the translation amount, a total number of word lines of the repetition array, a total number of bit lines of the repetition array, and a preset repetition rule; and controlling at least part of the translation array and at least part of the repetition array to translate by the translation amount along the translation direction, and controlling the repetition array to repeat for the number of repetitions along the repetition direction, to obtain the target expanded storage array.

2 . The method of claim 1 , wherein the translation array comprises a first translation array defined to translate in a first direction, a second translation array defined to translate in a second direction, and a third translation array defined to translate in the first direction and the second direction; and the calculating a translation amount of a translation array in a translation direction comprises:
calculating a first-direction translation amount of the first translation array in the first direction according to a difference between the total number of bit lines of the target expanded storage array and the total number of bit lines of the translation array; calculating a second-direction translation amount of the second translation array in the second direction according to a difference between the total number of word lines of the target expanded storage array and the total number of word lines of the translation array; and using a vector sum of the first-direction translation amount and the second-direction translation amount as a third-direction translation amount of the third translation array.

3 . The method of claim 2 , wherein the calculating a translation amount of a translation array in a translation direction further comprises:
determining a word line pitch and a bit line pitch of the storage array, wherein the word line pitch is an average distance between two adjacent word lines, and the bit line pitch is an average distance between two adjacent bit lines; and calculating the first-direction translation amount stretch_x and the second-direction translation amount stretch_y according to the following formulae:
stretch_ x =( N bitline− N corner b )*bitline_pitch; and

stretch_ y =( N wordline− N corner w )*wordline_pitch;

in the formulae, Nwordline is the total number of word lines of the target expanded storage array, Ncornerw is the total number of word lines of the translation array, Nbitline is the total number of bit lines of the target expanded storage array, Ncornerb is the total number of bit lines of the translation array, wordline_pitch is the word line pitch, and bitline_pitch is the bit line pitch.

4 . The method of claim 2 , wherein after controlling at least part of the translation array and at least part of the repetition array to translate by the translation amount along the translation direction, the repetition array is controlled to repeat for the number of repetitions along the repetition direction.

5 . The method of claim 2 , wherein the repetition array comprises a first repetition array to be repeated in the first direction, a second repetition array to be repeated in the second direction, and a third repetition array to be repeated in a vector sum direction of the first direction and the second direction; and the calculating a number of repetitions of a repetition array in a repetition direction comprises:
calculating a first number of repetitions of the first repetition array and the third repetition array in the first direction according to the difference between the total number of bit lines of the target expanded storage array and the total number of bit lines of the translation array; and calculating a second number of repetitions of the second repetition array and the third repetition array in the second direction according to the difference between the total number of word lines of the target expanded storage array and the total number of word lines of the translation array.

6 . The method of claim 5 , wherein the calculating the first number of repetitions and the second number of repetitions further comprises:
determining a number of bit lines Nb in the first repetition array and a number of word lines Nw in the second repetition array; and calculating the first number of repetitions repetition_x and the second number of repetitions repetition_y according to the following formulae:
repetition_ x =(( Nr bitline− N corner b )/ Nb )−1; and

repetition_ y =(( Nr wordline− N corner w )/ Nw )−1;

in the formulae, Nrwordline is the total number of word lines of the target expanded storage array, Nrbitline is the total number of bit lines of the target expanded storage array, Ncornerw is the total number of word lines of the translation array, and Ncornerb is the total number of bit lines of the translation array.

7 . The method of claim 1 , wherein the translation array comprises a corner array of the target expanded storage array.

8 . The method of claim 7 , wherein the translation array is a corner array of an initial array, and the translation array and the repetition array together form the initial array; and
the repetition array is located between adjacent translation arrays.

9 . The method of claim 7 , wherein the translation array is a corner array of an initial array, and the initial array is composed of the translation array and an intermediate array; and
a length of the repetition array in the repetition direction is less than a length of the intermediate array in the repetition direction, and a width of the repetition array in the repetition direction is equal to a width of the intermediate array in the repetition direction.

10 . The method of claim 2 , wherein:
the first direction is consistent with an extension direction of word lines; and the second direction is consistent with an extension direction of bit lines.

11 . A computer device, comprising a memory and a processor, the memory storing a computer program that, when executed by the processor, causes the processor to implement following:
acquiring a total number of word lines of a target expanded storage array and a total number of bit lines of the target expanded storage array; calculating a translation amount of a translation array in a translation direction according to the total number of word lines, the total number of bit lines, a total number of word lines of the translation array, a total number of bit lines of the translation array, and a preset translation rule, and calculating a number of repetitions of a repetition array in a repetition direction according to the translation amount, a total number of word lines of the repetition array, a total number of bit lines of the repetition array, and a preset repetition rule; and controlling at least part of the translation array and at least part of the repetition array to translate by the translation amount along the translation direction, and controlling the repetition array to repeat for the number of repetitions along the repetition direction, to obtain the target expande

Assignees

• Changxin Memory Tech Inc

Inventors

• Li Minghao
• Bai Li
• Chen Chuanjiang

Classifications

• G11C7/20

  Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title

• G06F30/323 Primary

  Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation · CPC title

• G11C5/025 Primary

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title