Systems and methods for defining memory sub-blocks

Patent metadata

Field	Value
Publication number	US-11487454-B2
Application number	US-201916704729-A
Country	US
Kind code	B2
Filing date	Dec 5, 2019
Priority date	Dec 5, 2019
Publication date	Nov 1, 2022
Grant date	Nov 1, 2022

Abstract

A method for memory block management includes identifying a first group of bit lines corresponding to memory blocks of a 3-dimensional memory array. The method also includes biasing the first group of bit lines to a first voltage using respective bit line biasing transistors. The method also includes identifying, for each memory block, respective sub-memory blocks corresponding to word lines of each memory block that intersect the first group of bit lines. The method also includes logically grouping memory addresses of memory cells for each respective sub-memory block associated with the first group of bit lines.

First claim

What is claimed is:

1. A method for memory block management, the method comprising:
identifying a first group of bit lines corresponding to memory blocks of a 3-dimensional memory array;
identifying a second group of bit lines corresponding to the memory blocks;
biasing the first group of bit lines to a first voltage using respective bit line biasing transistors;
biasing the second group of bit lines to a second voltage using respective bit line biasing transistors;
identifying, for each memory block, respective sub-memory blocks corresponding to word lines of each memory block that intersect the first group of bit lines;
logically grouping memory addresses of memory cells for each respective sub-memory block associated with the first group of bit lines;
identifying, for each memory block, respective sub-memory blocks corresponding to word lines of each memory block that intersect the second group of bit lines; and
logically grouping memory addresses of memory cells for each respective sub-memory block associated with the second group of bit lines.

2. The method of claim 1 , further comprising performing an operation on at least one sub-memory block.

3. The method of claim 2 , wherein the operation includes an erase operation.

4. The method of claim 1 , wherein the memory array includes a complementary metal-oxide semiconductor under the array memory structure (CUA).

5. The method of claim 1 , wherein the memory array includes a complementary metal-oxide semiconductor adjacent to the array memory structure (CAA).

6. The method of claim 1 , wherein each respective sub-memory block includes an 8-kilobyte sub-memory block.

7. The method of claim 1 , wherein each respective sub-memory block includes a 4-kilobyte sub-memory block.

8. The method of claim 1 , further comprising:
identifying, for each memory block, respective sub-memory blocks corresponding to word lines of each memory block that intersect the second group of bit lines; and
logically grouping memory addresses of memory cells for each respective sub-memory block associated with the second group of bit lines.

9. A controller comprising:
a bus interface in communication with a plurality of memory blocks of a 3-dimensional memory array that includes a complementary metal-oxide semiconductor under an array memory structure (CUA) or adjacent to the array memory structure (CAA); and
a processor configured to:
identify a first group of bit lines corresponding to the memory blocks;
bias the first group of bit lines to a first voltage using respective bit line biasing transistors;
identify, for each memory block, respective sub-memory blocks corresponding to word lines of each memory block that intersect the first group of bit lines; and
logically group memory addresses of memory cells for each respective sub-memory block associated with the first group of bit lines.

10. The controller of claim 9 , wherein the processor is further configured to perform an operation on at least one sub-memory block.

11. The controller of claim 10 , wherein the operation includes an erase operation.

12. The controller of claim 9 , wherein the complementary metal-oxide semiconductor is under the array memory structure (CUA).

13. The controller of claim 9 , wherein the complementary metal-oxide semiconductor is adjacent to the array memory structure (CAA).

14. The controller of claim 9 , wherein each respective sub-memory block includes an 8 -kilobyte sub-memory block.

15. The controller of claim 9 , wherein each respective sub-memory block includes a 4 -kilobyte sub-memory block.

16. The controller of claim 9 , wherein the processor is further configured to:
identify a second group of bit lines corresponding to the memory blocks; and
bias the second group of bit lines to a second voltage, different from the first voltage, using respective bit line biasing transistors.

17. The controller of claim 16 , wherein the processor is further configured to:
identify, for each memory block, respective sub-memory blocks corresponding to word lines of each memory block that intersect the second group of bit lines; and
logically group memory addresses of memory cells for each respective sub-memory block associated with the second group of bit lines.

18. A method for defining sub-memory blocks in a memory system, the method comprising:
identifying a first bit line group corresponding to memory blocks of a 3-dimensional memory array;
biasing the first bit line group to a first voltage using respective bit line biasing transistors;
identifying a second bit line group corresponding to the memory blocks;
biasing the second bit line group using a second voltage that is different than the first voltage using respective bit line transistors;
identifying, for each memory block, respective first and second sub-memory blocks corresponding to word lines of each memory block that intersect with respective ones of the first and second bit line groups; and
logically grouping memory addresses of memory cells for each respective sub-memory block.

19. The method of claim 18 , further comprising performing an erase operation on selected ones of the sub-memory blocks.

Assignees

• Sandisk Technologies Llc

Inventors

• Nishikawa Masatoshi
• Chibvongodze Hardwell

Classifications

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F13/1668 Primary

  Details of memory controller · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title