Semi-polling input/output completion mode for non-volatile memory express completion queue

Patent metadata

Field	Value
Publication number	US-12579088-B2
Application number	US-202418592026-A
Country	US
Kind code	B2
Filing date	Feb 29, 2024
Priority date	Nov 13, 2023
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

A system and method for using a semi-polling model to monitor a Non-Volatile Memory Express (NVMe) completion queue (CQ). The method, implemented at an interrupt thread, includes receiving an input/output (I/O) request from an application and submitting a submission queue (SQ) entry into an NVMe SQ in response to the I/O request. The method further includes registering for notifications from a polling thread after submitting the SQ entry and receiving, from the polling thread, a notification of the presence of a CQ entry within an NVMe CQ. Additionally, the method involves removing the CQ entry from the NVMe CQ and notifying the application of completion of the I/O request.

First claim

What is claimed:

1 . A method, implemented in a computer system that includes a processor system, comprising:
receiving, by an interrupt thread, an input/output (I/O) request from an application; submitting, by the interrupt thread, a submission queue (SQ) entry into a Non-Volatile Memory Express (NVMe) SQ in response to the I/O request; registering, by the interrupt thread, for notifications from a polling thread after submitting the SQ entry; responsive to the registering, identifying, by the polling thread, whether an NVMe completion queue (CQ) entry that corresponds to the SQ entry is present within an NVMe CQ without removing the CQ entry from the NVMe CQ; receiving, by the interrupt thread, a software interrupt from the polling thread, the software interrupt signaling a presence of a completion queue (CQ) entry within an NVMe CQ; removing, by the interrupt thread, the CQ entry from the NVMe CQ in response to receiving the software interrupt; and notifying, by the interrupt thread, the application of completion of the I/O request.

2 . The method of claim 1 , wherein the interrupt thread, the polling thread, and the application operate in user mode.

3 . The method of claim 1 , wherein the method further comprises ringing an SQ doorbell after submitting the SQ entry to the NVMe SQ.

4 . The method of claim 1 , wherein the method further comprises sleeping after registering for the notification from the polling thread.

5 . The method of claim 1 , wherein the method further comprises waking after receiving the notification of the presence of the CQ entry within the NVMe CQ.

6 . The method of claim 1 , wherein registering for the notification from the polling thread comprises registering for the software interrupt from the polling thread.

7 . A computer system comprising:
a processor system; and a computer storage medium that stores computer-executable instructions that are executable by the processor system to at least:
receive, by an interrupt thread, an input/output (I/O) request from an application;
submit, by the interrupt thread, a submission queue (SQ) entry into a Non-Volatile Memory Express (NVMe) SQ in response to the I/O request;
register, by the interrupt thread, for notifications from a polling thread after submitting the SQ entry, including registering for a software interrupt from the polling thread;
responsive to the registering, identifying, by the polling thread, whether an NVMe completion queue (CQ) entry that corresponds to the SQ entry is present within an NVMe CQ without removing the CQ entry from the NVMe CQ;
receive, by the interrupt thread, the software interrupt from the polling thread, the software interrupt signaling a presence of a completion queue (CQ) entry within an NVMe CQ, including receiving the software interrupt from the polling thread;
remove, by the interrupt thread, the CQ entry from the NVMe CQ in response to receiving the software interrupt; and
notify, by the interrupt thread, the application of completion of the I/O request.

8 . The computer system of claim 7 , wherein the interrupt thread, the polling thread, and the application operate in user mode.

9 . The computer system of claim 7 , wherein the computer-executable instructions are also executable by the processor system to ring an SQ doorbell after submitting the SQ entry to the NVMe SQ.

10 . The computer system of claim 7 , wherein the computer-executable instructions are also executable by the processor system to sleep after registering for the notification from the polling thread.

11 . The computer system of claim 7 , wherein the computer-executable instructions are also executable by the processor system to wake after receiving the notification of the presence of the CQ entry within the NVMe CQ.

12 . A computer-readable hardware storage medium that stores computer-executable instructions that are executable by a processor system to implement at an interrupt thread that is configured to at least:
receive, by the interrupt thread, an input/output (I/O) request from an application; submit, by the interrupt thread, a submission queue (SQ) entry into a Non-Volatile Memory Express (NVMe) SQ in response to the I/O request; register, by the interrupt thread, for notifications from a polling thread after submitting the SQ entry; responsive to the registering, identify, by the polling thread, whether an NVMe completion queue (CQ) entry that corresponds to the SQ entry is present within an NVMe CQ without removing the CQ entry from the NVMe CQ; receive, by the interrupt thread, a software interrupt from the polling thread, the software interrupt signaling a presence of the CQ entry within the NVMe CQ; remove, by the interrupt thread, the CQ entry from the NVMe CQ in response to receiving the software interrupt; and notify, by the interrupt thread, the application of completion of the I/O request.

13 . The computer-readable hardware storage medium of claim 12 , wherein the computer-executable instructions are also executable by the processor system to ring an SQ doorbell after submitting the SQ entry to the NVMe SQ.

14 . The computer-readable hardware storage medium of claim 12 , wherein the computer-executable instructions are also executable by the processor system to sleep after registering for the notification from the polling thread.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Jin Ming
• Makhervaks Vadim
• Dai Ji
• Yan Tengda
• Yi Yuan
• Yin Chuanjun
• Lee Scott Chao-Chueh

Classifications

• G06F13/225

  with priority control · CPC title

• G06F13/22

  using successive scanning, e.g. polling (G06F13/24 takes precedence) · CPC title

• G06F13/26 Primary

  with priority control · CPC title