Application programming interface to share memory between groups of blocks of threads

US12578993B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12578993-B2
Application numberUS-202217955175-A
CountryUS
Kind codeB2
Filing dateSep 28, 2022
Priority dateJul 29, 2022
Publication dateMar 17, 2026
Grant dateMar 17, 2026

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to cause memory to be shared between two or more groups of blocks of threads.

First claim

Opening claim text (preview).

What is claimed is: 1 . A processor comprising: one or more circuits to perform an application programming interface (API) to cause memory to be shared between two or more groups of blocks of threads. 2 . The processor of claim 1 , wherein the two or more groups of blocks of threads are groups within a software kernel. 3 . The processor of claim 1 , wherein the two or more groups of blocks of threads are groups within a grid of blocks of threads. 4 . The processor of claim 1 , wherein the two or more groups of blocks of threads are partitions of a partitioning of blocks of threads. 5 . The processor of claim 1 , wherein the memory is memory of a graphics processing unit (GPU). 6 . The processor of claim 1 , wherein the API is to cause at least one thread of one group of blocks of threads to be able to access a memory location accessible to at least one thread of another group of blocks of threads. 7 . The processor of claim 1 , wherein the API is to cause at least one thread of one group of blocks of threads to provide a memory address of the memory to be shared to the two or more groups of blocks of threads. 8 . The processor of claim 1 , wherein the API is to cause at least one thread of a first group of blocks of threads to calculate a memory address of the memory to be shared based, at least in part, on an identifier of a block of the first group of blocks of threads. 9 . The processor of claim 1 , wherein the API is to cause at least one thread of a first group of blocks of threads to calculate a memory address of the memory to be shared based, at least in part, on an identifier of the first group of blocks of threads. 10 . A computer-implemented method comprising: performing an application programming interface (API) to cause memory to be shared between two or more groups of blocks of threads. 11 . The computer-implemented method of claim 10 , wherein the two or more groups of blocks of threads are groups within a software kernel. 12 . The computer-implemented method of claim 10 , wherein the two or more groups of blocks of threads are groups within a grid of blocks of threads. 13 . The computer-implemented method of claim 10 , wherein the two or more groups of blocks of threads are partitions of a partitioning of blocks of threads. 14 . The computer-implemented method of claim 10 , wherein the memory is memory of a graphics processing unit (GPU). 15 . The computer-implemented method of claim 10 , wherein the API is to cause at least one thread of one group of blocks of threads to be able to access a memory location accessible to at least one thread of another group of blocks of threads. 16 . The computer-implemented method of claim 10 , wherein the API is to cause at least one thread of one group of blocks of threads to provide a memory address of the memory to be shared to the two or more groups of blocks of threads. 17 . The computer-implemented method of claim 10 , wherein the API is to cause at least one thread of a first group of blocks of threads to calculate a memory address of the memory to be shared based, at least in part, on an identifier of a block of the first group of blocks of threads. 18 . The computer-implemented method of claim 10 , wherein the API is to cause at least one thread of a first group of blocks of threads to calculate a memory address of the memory to be shared based, at least in part, on an identifier of the first group of blocks of threads. 19 . A computer system comprising: one or more processors and memory storing executable instructions that, if performed by the one or more processors, are to perform an application programming interface (API) to cause memory to be shared between two or more groups of blocks of threads. 20 . The computer system of claim 19 , wherein the two or more groups of blocks of threads are groups within a software kernel. 21 . The computer system of claim 19 , wherein the two or more groups of blocks of threads are groups within a grid of blocks of threads. 22 . The computer system of claim 19 , wherein the two or more groups of blocks of threads are partitions of a partitioning of blocks of threads. 23 . The computer system of claim 19 , wherein the memory is memory of a graphics processing unit (GPU). 24 . The computer system of claim 19 , wherein the API is to cause at least one thread of one group of blocks of threads to be able to access a memory location accessible to at least one thread of another group of blocks of threads. 25 . The computer system of claim 19 , wherein the API is to cause at least one thread of one group of blocks of threads to provide a memory address of the memory to be shared to the two or more groups of blocks of threads. 26 . The computer system of claim 19 , wherein the API is to cause at least one thread of a first group of blocks of threads to calculate a memory address of the memory to be shared based, at least in part, on an identifier of a block of the first group of blocks of threads. 27 . The computer system of claim 19 , wherein the API is to cause at least one thread of a first group of blocks of threads to calculate a memory address of the memory to be shared based, at least in part, on an identifier of the first group of blocks of threads. 28 . A machine-readable medium having stored thereon a set of instructions, which if performed by one or more processors, are to perform an application programming interface (API) to cause memory to be shared between two or more groups of blocks of threads. 29 . The machine-readable medium of claim 28 , wherein the two or more groups of blocks of threads are groups within a software kernel. 30 . The machine-readable medium of claim 28 , wherein the two or more groups of blocks of threads are groups within a grid of blocks of threads. 31 . The machine-readable medium of claim 28 , wherein the two or more groups of blocks of threads are partitions of a partitioning of blocks of threads. 32 . The machine-readable medium of claim 28 , wherein the memory is memory of a graphics processing unit (GPU). 33 . The machine-readable medium of claim 28 , wherein the API is to cause at least one thread of one group of blocks of threads to be able to access a memory location accessible to at least one thread of another group of blocks of threads. 34 . The machine-readable medium of claim 28 , wherein the API is to cause at least one thread of one group of blocks of threads to provide a memory address of the memory to be shared to the two or more groups of blocks of threads. 35 . The machine-readable medium of claim 28 , wherein the API is to cause at least one thread of a first group of blocks of threads to calculate a memory address of the memory to be shared based, at least in part, on an identifier of a block of the first group of blocks of threads. 36 . The machine-readable medium of claim 28 , wherein the API is to cause at least one thread of a first group of blocks of threads to calculate a memory address of the memory to be shared based, at least in part, on an identifier of the first group of blocks of threads.

Assignees

Inventors

Classifications

  • considering the load · CPC title

  • Barrier synchronisation · CPC title

  • to perform conditional operations, e.g. using predicates or guards · CPC title

  • Buffers; Shared memory; Pipes · CPC title

  • G06F8/456Primary

    Parallelism detection · CPC title

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Frequently asked questions

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What does patent US12578993B2 cover?
Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to cause memory to be shared between two or more groups of blocks of threads.
Who is the assignee on this patent?
Nvidia Corp
What technology area does this patent fall under?
Primary CPC classification G06F8/456. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 17 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).