Power semiconductor module and power converter

Patent metadata

Field	Value
Publication number	US-12575431-B2
Application number	US-202519293852-A
Country	US
Kind code	B2
Filing date	Aug 7, 2025
Priority date	Apr 1, 2024
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

A power semiconductor module may comprise a common drain pad, a first power semiconductor device on a first region of the common drain pad, a second power semiconductor device on a second region of the common drain pad, a molding layer surrounding lateral parts of the first power semiconductor device and the second power semiconductor device on a peripheral region of the common drain pad, a common gate pad on the first power semiconductor device and the second power semiconductor device, and a source pad on the first power semiconductor device and the second power semiconductor device. The source pad may surround at least two outer lateral parts of the common gate pad.

First claim

The invention claimed is:

1 . A power semiconductor module, comprising: a common drain pad; a first power semiconductor device on a first region of the common drain pad; a second power semiconductor device on a second region of the common drain pad; a common gate pad on the first power semiconductor device and the second power semiconductor device; and a source pad on the first power semiconductor device and the second power semiconductor device, wherein the common drain pad is configured to be electrically connected to a first drain electrode of the first power semiconductor device and a second drain electrode of the second power semiconductor device, wherein the common gate pad is configured to be electrically connected to a first gate electrode of the first power semiconductor device and a second gate electrode of the second power semiconductor device, wherein the source pad is configured to be electrically connected to a first source electrode of the first power semiconductor device and a second source electrode of the second power semiconductor device, and wherein the source pad is configured to surround at least two outer lateral parts of the common gate pad, wherein the source pad comprises a common source pad that vertically overlaps the first power semiconductor device and the second power semiconductor device.

2 . The power semiconductor module of claim 1 , wherein the common source pad has an opening, and the common gate pad is positioned in the opening.

3 . The power semiconductor module of claim 1 , wherein the common gate pad comprises a first short-lateral part and a second short-lateral part in one direction, and a first long-lateral part and a second long-lateral part in a direction perpendicular to the one direction.

4 . The power semiconductor module of claim 3 , wherein the common source pad is positioned on the first short-lateral part, the second short-lateral part, and the first long-lateral part of the common gate pad.

5 . The power semiconductor module of claim 4 , wherein the common source pad is positioned on the second long-lateral part of the common gate pad.

6 . The power semiconductor module of claim 3 , wherein the first short-lateral part of the common gate pad is positioned between the first gate electrode and the first source electrode, and
wherein the second short-lateral part of the common gate pad is positioned between the second gate electrode and the second source electrode.

7 . The power semiconductor module of claim 1 , wherein the source pad comprises a first source pad and a second source pad that vertically overlap the first source electrode of the first power semiconductor device and the second source electrode of the second power semiconductor device, respectively.

8 . The power semiconductor module of claim 1 , further comprising:
a Kelvin source pad spaced apart from the source pad on the first power semiconductor device and the second power semiconductor device.

9 . The power semiconductor module of claim 1 , wherein a size of the common gate pad is greater than a size of the first gate electrode of the first power semiconductor device or a size of the second gate electrode of the second power semiconductor device.

10 . A power semiconductor module, comprising: a common drain pad; a first power semiconductor device on a first region of the common drain pad; a second power semiconductor device on a second region of the common drain pad; a common gate pad on the first power semiconductor device and the second power semiconductor device; and a source pad on the first power semiconductor device and the second power semiconductor device, wherein the common drain pad is configured to be electrically connected to a first drain electrode of the first power semiconductor device and a second drain electrode of the second power semiconductor device, wherein the common gate pad is configured to be electrically connected to a first gate electrode of the first power semiconductor device and a second gate electrode of the second power semiconductor device, wherein the source pad is configured to be electrically connected to a first source electrode of the first power semiconductor device and a second source electrode of the second power semiconductor device, and wherein the common gate pad vertically overlaps at least one of the first source electrode and the second source electrode, wherein the source pad comprises a common source pad that vertically overlaps the first power semiconductor device and the second power semiconductor device.

11 . The power semiconductor module of claim 10 , wherein the source pad comprises a first source pad and a second source pad that vertically overlap the first source electrode of the first power semiconductor device and the second source electrode of the second power semiconductor device, respectively.

12 . The power semiconductor module of claim 10 , wherein the common gate pad is disposed across the first source electrode and the first gate electrode and the second gate electrode and the second source electrode along one direction on the first region of the common drain pad.

13 . The power semiconductor module of claim 10 , wherein the common source pad is disposed across the first source electrode and the second source electrode along one direction on the second region of the common drain pad.

14 . The power semiconductor module of claim 10 , wherein an area of the common source pad is greater than an area of the first source electrode of the first power semiconductor device or an area of the second source electrode of the second power semiconductor device.

15 . The power semiconductor module of claim 10 , wherein an area of the common drain pad is greater than a sum of an area of the common gate pad and an area of the common source pad.

16 . The power semiconductor module of claim 10 , further comprising:
a Kelvin source pad spaced from the source pad on the first power semiconductor device and the second power semiconductor device.

17 . A power converter, comprising:
a first substrate; a second substrate; and a plurality of power semiconductor modules between the first substrate and the second substrate, wherein the plurality of power semiconductor modules each comprise:
a common drain pad;
a first power semiconductor device on a first region of the common drain pad;
a second power semiconductor device on a second region of the common drain pad;
a common gate pad on the first power semiconductor device and the second power semiconductor device; and
a common source pad on the first power semiconductor device and the second power semiconductor device,
wherein the common source pad is configured to surround at least two lateral parts of the common gate pad, wherein in some modules of the plurality of power semiconductor modules, the common drain pad is configured to be electrically connected to the first substrate, the common gate pad and the common source pad are each electrically connected to the second substrate, and wherein in the remaining modules of the plurality of power semiconductor modules, the common drain pad is configured to be electrically connected to the second substrate, and the common gate pad and the common source pad are each electrically connected to the first substrate.

18 . The power converter of claim 17 , further comprising:
a plurality of terminals connected to each of the first substrate and the second substrate.

Assignees

• Lx Semicon Co Ltd

Inventors

• Kim Deog Soo
• Kim Tae Ryong
• Lee Myoung Ho
• Kim You Suk

Classifications

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H05K2201/042

  Stacked spaced PCBs; Planar parts of folded flexible circuits having mounted components in between or spaced from each other · CPC title

• H05K1/181

  associated with surface mounted components · CPC title

• H05K1/145

  Arrangements wherein electric components are disposed between and simultaneously connected to two planar printed circuit boards, e.g. Cordwood modules · CPC title