Semiconductor structure having deep trench capacitor and method of manufacturing thereof

Patent metadata

Field	Value
Publication number	US-12575414-B2
Application number	US-202217817108-A
Country	US
Kind code	B2
Filing date	Aug 3, 2022
Priority date	Aug 3, 2022
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

The semiconductor structure includes a substrate defined with an array region and a seal ring region surrounding the array region, and including a recess extending into the substrate; a capacitor cell disposed within the array region; and a seal ring disposed within the seal ring region, and including a capacitor structure at least partially disposed within the recess, and an interconnect structure disposed over the capacitor structure, wherein the interconnect structure is electrically coupled to the substrate.

First claim

What is claimed is:

1 . A semiconductor structure, comprising:
a substrate defined with an array region and a seal ring region surrounding the array region, and including a first surface, a second surface opposite to the first surface, and a recess extending from the first surface toward the second surface; a capacitor cell disposed within the array region; and a seal ring disposed within the seal ring region, and including a capacitor structure at least partially disposed within the recess and at least partially disposed on the first surface, and an interconnect structure disposed over the capacitor structure, wherein the interconnect structure is electrically coupled to first surface of the substrate.

2 . The semiconductor structure of claim 1 , wherein the interconnect structure is connected to an electrical ground.

3 . The semiconductor structure of claim 1 , wherein the capacitor structure of the seal ring is a dummy capacitor.

4 . The semiconductor structure of claim 1 , wherein the capacitor structure of the seal ring is electrically isolated from the capacitor cell.

5 . The semiconductor structure of claim 1 , wherein the capacitor structure includes an electrode at least partially disposed within the recess and over the substrate.

6 . The semiconductor structure of claim 5 , wherein the interconnect structure is electrically coupled to the electrode of the capacitor structure.

7 . The semiconductor structure of claim 5 , wherein the capacitor structure includes an isolation layer covering the electrode.

8 . The semiconductor structure of claim 7 , wherein the interconnect structure includes a conductive via extending through the isolation layer and contacting the electrode of the capacitor structure.

9 . The semiconductor structure of claim 1 , further comprising a dielectric layer disposed over the substrate and the capacitor structure, wherein the interconnect structure includes a conductive via extending through the dielectric layer and contacting the substrate.

10 . The semiconductor structure of claim 1 , wherein a distance between the capacitor cell and the seal ring is substantially greater than 0.1 um.

11 . A semiconductor structure, comprising:
a substrate defined with an array region and a seal ring region surrounding the array region, and including a first surface, a second surface opposite to the first surface, and a recess extending into the substrate; a capacitor cell disposed within the array region and partially surrounded by the substrate; and a seal ring disposed within the seal ring region, and including a capacitor structure at least partially disposed within the recess and at least partially disposed on the first surface, and an interconnect structure disposed over the capacitor structure; and a dielectric layer on the first surface of the substrate and covering the capacitor structure, wherein the interconnect structure extends through the dielectric layer and is coupled to the first surface of the substrate.

12 . The semiconductor structure of claim 11 , wherein the capacitor cell is electrically isolated from the capacitor structure of the seal ring.

13 . The semiconductor structure of claim 11 , wherein the capacitor structure includes an electrode at least partially disposed within the recess and over the substrate.

14 . The semiconductor structure of claim 13 , wherein the interconnect structure includes a first conductive via coupled to the electrode.

15 . The semiconductor structure of claim 14 , wherein the interconnect structure includes a second conductive via coupled to the substrate.

16 . The semiconductor structure of claim 15 , wherein a length of the first conductive via is substantially shorter than a length of the second conductive via.

17 . The semiconductor structure of claim 15 , wherein the dielectric layer is disposed over the capacitor cell and the first conductive via and the second conductive via are surrounded by the dielectric layer.

18 . The semiconductor structure of claim 11 , wherein a depth of a portion of the capacitor cell laterally surrounded by the substrate is substantially equal to a depth of the recess.

19 . A semiconductor structure, comprising:
a substrate defined with an array region and a seal ring region surrounding the array region, and including a first surface, a second surface opposite to the first surface, and a recess within the seal ring region and extending into the substrate; a capacitor structure at least partially disposed within the recess and at least partially disposed on the first surface; a dielectric layer over the substrate and the capacitor structure; and a conductive via extending through the dielectric layer and contacting the first surface of the substrate.

20 . The semiconductor structure of claim 19 , wherein the conductive via is isolated from the capacitor structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Jen-Yuan

Classifications

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H10D1/716

  having vertical extensions · CPC title

• H10D1/042 Primary

  using deposition processes to form electrode extensions · CPC title

• H10W42/00 Primary

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W74/147

  the encapsulations being multilayered · CPC title