Metal lines of hybrid heights

Patent metadata

Field	Value
Publication number	US-12575397-B2
Application number	US-202217832584-A
Country	US
Kind code	B2
Filing date	Jun 4, 2022
Priority date	Feb 25, 2022
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first interconnect layer over a substrate, the first interconnect layer including a first conductive feature and a second conductive feature, forming a patterned mask on the first interconnect layer, one or more openings in the patterned mask overlaying the second conductive feature, recessing the second conductive feature through the one or more openings in the patterned mask, and forming a second interconnect layer over the first interconnect layer. The second interconnect layer includes a first via in contact with the first conductive feature and a second via in contact with the second conductive feature.

First claim

What is claimed is:

1 . A method of fabricating a semiconductor device, comprising:
forming a first interconnect layer over a substrate, the first interconnect layer including a first conductive feature and a second conductive feature, wherein the forming of the first interconnect layer includes:
depositing a conductive layer over the substrate,
patterning the conductive layer, thereby forming the first and second conductive features, and
depositing a dielectric material between the first and second conductive features;
forming a patterned mask on the first interconnect layer, one or more openings in the patterned mask overlaying the second conductive feature; recessing the second conductive feature through the one or more openings in the patterned mask; and forming a second interconnect layer over the first interconnect layer, the second interconnect layer having a first via in contact with the first conductive feature and a second via in contact with the second conductive feature.

2 . The method of claim 1 , wherein after the recessing of the second conductive feature, a top surface of the second conductive feature is below a top surface of the first conductive feature.

3 . The method of claim 2 , wherein the top surface of the second conductive feature is below the top surface of the first conductive feature for at least 3 nanometer (nm).

4 . The method of claim 1 , wherein a vertical length of the second via is larger than a vertical length of the first via.

5 . The method of claim 1 , wherein the first conductive feature corresponds to a power grid of the semiconductor device, and wherein the second conductive feature corresponds to a signal line of the semiconductor device.

6 . The method of claim 1 , wherein the first conductive feature corresponds to a bit line in a memory circuit of the semiconductor device, and wherein the second conductive feature corresponds to a word line of the memory circuit.

7 . The method of claim 1 , further comprising:
recessing a third conductive feature in the second interconnect layer, wherein the third conductive feature is in contact with the second via.

8 . The method of claim 1 , wherein the conductive layer includes a noble metal.

9 . The method of claim 1 , wherein the depositing of the dielectric material caps an air gap between the first and second conductive features.

10 . The method of claim 1 , further comprising:
prior to the forming of the patterned mask, depositing an etch stop layer over the first interconnect layer, wherein after the forming of the second interconnect layer, a bottom portion of the first via is in contact with the etch stop layer and the second via is free of contact with the etch stop layer.

11 . A method, comprising:
forming a first metal line and a second metal line over a substrate, the first and second metal lines having a same thickness; depositing an etch stop layer over the first and second metal lines; removing a portion of the etch stop layer, thereby exposing the second metal line; partially removing the second metal line, such that the second metal line becomes thinner than the first metal line; depositing a dielectric layer over the first and second metal lines; and forming a third metal line and a via in the dielectric layer, the via connecting the third metal line with one of the first and second metal lines.

12 . The method of claim 11 , wherein the first and second metal lines extend lengthwise in a first direction, and wherein the third metal line extends lengthwise in a second direction perpendicular to the first direction.

13 . The method of claim 11 , wherein the first and second metal lines include a first metal, and wherein the third metal line includes a second metal different from the first metal.

14 . The method of claim 13 , wherein the first metal is a noble metal.

15 . The method of claim 11 , wherein the via connects the third metal line with the first metal line, and wherein a sidewall of the via is in contact with the etch stop layer.

16 . The method of claim 11 , wherein the via connects the third metal line with the second metal line, and wherein the via is free of contact with the etch stop layer.

17 . The method of claim 11 , wherein the first metal line corresponds to a power line of a memory device, and wherein the second metal line corresponds to a signal line of the memory device.

18 . A method, comprising:
forming a memory cell; forming a first interconnect layer over the memory cell, the first interconnect layer including a first metal line coupled to a power supply port or a bit line port of the memory cell and a second metal line coupled to a word line port of the memory cell, a thickness of the first metal line being equal to a thickness of the second metal line; reducing the thickness of the second metal line, such that the thickness of the first metal line is greater than the thickness of the second metal line; and forming a second interconnect layer over the first interconnect layer, the second interconnect layer including a first via coupled to the first metal line and a second via coupled to the second metal line.

19 . The method of claim 18 , wherein a height of the first via is less than a height of the second via.

20 . The method of claim 18 , wherein the first and second metal lines include a noble metal.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Chia-Tien
• Chu Wei-Chen
• Liao Yu-Chieh
• Chen Hsin-Ping

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/43

  Layouts of interconnections · CPC title