Array substrates and display devices

Patent metadata

Field	Value
Publication number	US-12575239-B2
Application number	US-202218037040-A
Country	US
Kind code	B2
Filing date	Feb 24, 2022
Priority date	Feb 24, 2022
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

The present application provides an array substrate and a display device. The array substrate includes a base, a first insulating layer located on the base, a first conductive layer located on the first insulating layer, a second insulating layer located on the first conductive layer, and an electronic element located on the first conductive layer. The first insulating layer is provided with a plurality of first openings. The first conductive layer includes a plurality of pads, each of which is at least partially located in one of the first openings. The second insulating layer is provided with a plurality of second openings. An orthographic projection of each first opening on the base falls into that of one of the second openings on the base. The electronic element includes an electronic element body, and a plurality of pins located on a side of the electronic element body toward the base. Each of the pins is at least partially located in the first opening and the second opening, and is soldered with the pad. The display device includes the array substrate.

First claim

The invention claimed is:

1 . An array substrate, comprising:
a base; a first insulating layer located on the base and provided with a plurality of first openings; a first conductive layer located on the first insulating layer and comprising a plurality of pads, wherein each of the plurality of pads is at least partially located in one of the plurality of first openings; a second insulating layer located on the first conductive layer and provided with second openings, wherein an orthographic projection of each of the plurality of first openings onto the base is within an orthographic projection of one of the second openings onto the base; an electronic element located on the first conductive layer, wherein the electronic element comprises an electronic element body and a plurality of pins located on a side of the electronic element body toward the base, and each of the plurality of pins is at least partially located in the corresponding first opening and the corresponding second opening, and is soldered with the corresponding pad; wherein the second insulating layer comprises a first sub-insulating layer, for each of the second openings, the second opening comprises a first sub-opening disposed in the first sub-insulating layer; the electronic element body is at least partially located in the corresponding first sub-opening, and an orthographic projection of the electronic element body onto the base is within an orthographic projection of the corresponding first sub-opening onto the base; and an orthographic projection of each of the first sub-openings onto the base covers orthographic projections of a plurality of first openings onto the base; wherein the array substrate further comprises: a protective material filled between the electronic element body and opening walls of the first sub-opening.

2 . The array substrate according to claim 1 , wherein the first insulating layer comprises a first organic layer.

3 . The array substrate according to claim 2 , further comprising: a first inorganic layer located between the first organic layer and the first conductive layer.

4 . The array substrate according to claim 3 , wherein orthographic projections of the plurality of pads onto the base are within an orthographic projection of the first inorganic layer onto the base.

5 . The array substrate according to claim 3 , wherein a thickness of the first inorganic layer is smaller than a thickness of the first organic layer.

6 . The array substrate according to claim 1 , wherein the protective material is a soldering flux.

7 . The array substrate according to claim 1 , wherein the first sub-insulating layer comprises a second organic layer.

8 . The array substrate according to claim 1 , wherein the second insulating layer further comprises a second sub-insulating layer located on a side of the first sub-insulating layer toward the base,
for each of the second openings, the second opening comprises a plurality of second sub-openings disposed in the second sub-insulating layer; the orthographic projection of each of the plurality of first openings onto the base is within an orthographic projection of one of the plurality of second sub-openings onto the base, and the orthographic projection of each of the first sub-openings onto the base covers orthographic projections of the plurality of second sub-openings onto the base.

9 . The array substrate according to claim 8 , wherein an edge of the orthographic projection of each of the plurality of first openings onto the base is inside an edge of the orthographic projection of one of the plurality of second sub-openings onto the base.

10 . The array substrate according to claim 8 , wherein the second sub-insulating layer comprises a second inorganic layer.

11 . The array substrate according to claim 1 , wherein the electronic element comprises an inorganic light emitting diode with a size of hundred microns or below.

12 . The array substrate according to claim 1 , further comprising:
a third insulating layer located on a side of the first insulating layer toward the base, and a second conductive layer located between the third insulating layer and the base.

13 . The array substrate according to claim 12 , wherein the third insulating layer comprises a third organic layer.

14 . A display device, comprising: the array substrate according to claim 1 .

15 . The array substrate according to claim 1 , wherein the electronic element comprises a driver chip with a size of hundred microns or below.

16 . An array substrate, comprising:
a base; a first insulating layer located on the base and provided with a plurality of first openings; a first conductive layer located on the first insulating layer and comprising a plurality of pads, wherein each of the plurality of pads is at least partially located in one of the plurality of first openings; a second insulating layer located on the first conductive layer and provided with second openings, wherein an orthographic projection of each of the plurality of first openings onto the base is within an orthographic projection of one of the second openings onto the base; an electronic element located on the first conductive layer, wherein the electronic element comprises an electronic element body and a plurality of pins located on a side of the electronic element body toward the base, and each of the plurality of pins is at least partially located in the corresponding first opening and the corresponding second opening, and is soldered with the corresponding pad; wherein the second insulating layer comprises a first sub-insulating layer, for each of the second openings, the second opening comprises a first sub-opening disposed in the first sub-insulating layer; the electronic element body is at least partially located in the corresponding first sub-opening, and an orthographic projection of the electronic element body onto the base is within an orthographic projection of the corresponding first sub-opening onto the base; and an orthographic projection of each of the first sub-openings onto the base covers orthographic projections of a plurality of first openings onto the base; wherein the second insulating layer further comprises a second sub-insulating layer located on a side of the first sub-insulating layer toward the base, for each of the second openings, the second opening comprises a plurality of second sub-openings disposed in the second sub-insulating layer; the orthographic projection of each of the plurality of first openings onto the base is within an orthographic projection of one of the plurality of second sub-openings onto the base, and the orthographic projection of each of the first sub-openings onto the base covers orthographic projections of the plurality of second sub-openings onto the base.

Assignees

• Hefei Boe Ruisheng Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Qin Jianwei
• Gao Liang
• Zhang Bing
• Lv Chaoren
• Sun Yiding
• Cha Huangfei

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H10D86/411

  characterised by materials, geometry or structure of the substrates · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10H20/857 Primary

  Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title

• H01L25/167

  Electricity · mapped topic