Semiconductor structure and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-2016190080-A1
Application number	US-201514957027-A
Country	US
Kind code	A1
Filing date	Dec 2, 2015
Priority date	Dec 31, 2014
Publication date	Jun 30, 2016
Grant date	—

Abstract

The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.

First claim

What is claimed is:

1 . A method of fabricating a semiconductor structure, comprising:
providing a chip having a plurality of conductive pads and a protective layer that has a plurality of protective-layer openings, with a portion of each of the conductive pads exposed from each of the protective-layer openings; forming a metal layer on the protective layer, and electrically connecting the metal layer to the conductive pads; forming on a portion of the metal layer a first passivation layer that has a plurality of first openings, with a portion of the metal layer exposed from the first openings; forming a plurality of conductive pillars on the exposed portion of the metal layer in the first openings; and removing a portion of the metal layer, with a portion of the metal layer under the conductive pillars and the first passivation layer remained.

2 . The method of claim 1 , wherein the first openings are positioned above the protective-layer opening, and each of the first openings has a width greater than or equal to a width of each of the protective-layer openings.

3 . The method of claim 1 , wherein the first passivation layer between two neighboring ones of the conductive pads is discontinuous.

4 . The method of claim 1 ., wherein the remained portion of the metal layer has a lateral side flush with a lateral side of the first passivation layer.

5 . The method of claim 1 , wherein the metal layer is made of titanium and copper.

6 . The method of claim 1 wherein the conductive pillars are copper pillars.

7 . The method of claim 1 , further comprising, prior to removing a portion of the metal layer, forming conductive material on a top surface of each of the conductive pillars.

8 . The method of claim 1 , wherein the remained portion of the metal layer under each of the conductive pillars is wider than each of the conductive pillars.

9 . The method of claim 1 , further comprising, after providing a chip having a plurality of conductive pads and a protective layer, forming a second passivation layer on the protective layer and the conductive pads, forming in the second passivation layer a plurality of second openings, with a portion of each of the conductive pads exposed from each of the second openings, and forming the metal layer on the exposed portion of each of the conductive pads in each of the second openings and on the second passivation layer.

10 . The method of claim 9 , further comprising, after forming a second passivation layer on the protective layer and the conductive pads, forming a re-distribution layer on the second passivation layer and on the exposed portion of each of the conductive pads in each of the second openings, forming a third passivation layer on the re-distribution layer, and forming the metal layer on the re-distribution layer.

11 . The method of claim 10 , wherein the third passivation layer has a plurality of third openings that are dislocated with respect to the second openings, and a portion of the re-distribution layer is exposed from the third openings.

12 . The method of claim 1 , wherein a portion of the first passivation layer is embedded into the conductive pillars when the conductive pillars are formed.

13 . The method of claim 1 , wherein the conductive pillars are formed by:
forming a resist layer on the metal layer and the first passivation layer, and forming a plurality of openings in the resist layer, with a portion of the metal layer exposed from the openings; forming the conductive pillars on the exposed portion of the metal layer via the openings of the resist layer; and removing the resist layer.

14 . A method of fabricating a semiconductor structure, comprising:
providing a chip having a plurality of conductive pads and a protective layer that has a plurality of protective-layer openings, with a portion of each of the conductive pads exposed from each of the protective-layer openings; forming a metal layer on the protective layer, and electrically connecting the metal layer to the conductive pads, with a portion of the protective layer exposed from the metal layer; forming on a portion of the metal layer and on the protective layer a first passivation layer that covers a lateral side of the metal layer, and forming a plurality of first openings in the first passivation layer, with a portion of the metal layer exposed from the first openings; and forming a plurality of conductive pillars on the exposed portion of the metal layer in the first openings.

15 . The method of claim 14 , wherein the first openings are positioned above the protective-layer opening, and each of the first openings has a width greater than or equal to a width of each of the protective-layer openings.

16 . The method of claim 14 , wherein the metal layer is formed by:
forming a metal material on the conductive pads and the protective layer; forming a resist layer on the metal material, with a portion of the metal material exposed therefrom; removing the exposed portion of the metal material, so as for a remaining portion of the metal material to form the metal layer; and removing the resist layer.

17 . The method of claim 14 , wherein the metal layer is made of titanium and copper.

18 . The method of claim 14 , wherein the conductive pillars are copper pillars.

19 . The method of claim 14 , further comprising forming a conductive material on a top surface of each of the conductive pillars.

20 . The method of claim 14 , wherein the metal layer under each of the conductive pillars has a width greater than or equal to a width of each of the conductive pillars.

21 . The method of claim 14 , further comprising, after providing a chip having a plurality of conductive pads and a protective layer, forming a second passivation layer on the protective layer and conductive pads, forming a plurality of second openings in the second passivation layer, with a portion of each of the conductive pads exposed from each of the second openings, and forming the metal layer on the exposed portion of the conductive pads in the second opening and on the second passivation layer.

22 . The method of claim 21 , further comprising, after forming the second passivation layer on the protective layer and die conductive pads, forming ore-distribution layer on the second passivation layer and on the exposed portion of each of the conductive pads in the second openings, forming a third passivation layer on there-distribution layer, and forming the metal layer on the re-distribution layer.

23 . The method of claim 22 , wherein the third passivation layer has a plurality of third openings that are dislocated with respect to the second openings, and a portion of the re-distribution layer is exposed from the third openings.

24 . The method of claim 14 , wherein a portion of the first passivation layer is embedded into the conductive pillars when the conductive pillars are formed.

25 . The method of claim 14 , wherein the conductive pillars are formed by:
forming a resist layer on the protective layer, and the first passivation layer, and forming a plurality of openings in the resist layer, with a portion of the metal layer exposed from the openings; forming the conductive pillars on the exposed portion of the metal layer in the openings of the resist layer; and removing the resist layer.

26 . The method of claim 14 , wherein the first passivati

Assignees

• Siliconware Precision Industries Co Ltd

Inventors

• Chen Yi-Cheih
• Sun Sung-Huan
• Chang Cheng-An
• Wu Chien-Hung
• Huang Fu-Tang

Classifications

• H10W72/01953

  by etching · CPC title

• H10W72/01938

  in gaseous form, e.g. by CVD or PVD · CPC title

• H10W72/01908

  using permanent auxiliary members, e.g. using alignment marks · CPC title

• H10W72/01257

  by reflowing · CPC title

• H10W72/01255

  by using masks · CPC title