Gate-all-around integrated circuit structures having doped subfin

Patent metadata

Field	Value
Publication number	US-12575151-B2
Application number	US-202117482870-A
Country	US
Kind code	B2
Filing date	Sep 23, 2021
Priority date	Sep 23, 2021
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

Gate-all-around integrated circuit structures having a doped subfin, and methods of fabricating gate-all-around integrated circuit structures having a doped subfin, are described. For example, an integrated circuit structure includes a subfin structure having well dopants. A vertical arrangement of horizontal semiconductor nanowires is over the subfin structure. A gate stack is surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires, the gate stack overlying the subfin structure. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires.

First claim

What is claimed is:

1 . An integrated circuit structure, comprising:
a subfin structure having well dopants with a concentration of greater than 3E18 atoms/cm 3 ; a vertical arrangement of horizontal semiconductor nanowires over the subfin structure; a silicon carbide dielectric structure vertically between the vertical arrangement of horizontal semiconductor nanowires and the subfin structure, the silicon carbide dielectric structure vertically spaced apart from a bottommost nanowire of the vertical arrangement of horizontal semiconductor nanowires; a gate stack surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires, wherein the gate stack is in contact with the silicon carbide dielectric structure; and a pair of epitaxial source or drain structures at first and second ends of the vertical arrangement of horizontal semiconductor nanowires.

2 . The integrated circuit structure of claim 1 , wherein the well dopants are N-type dopants, and the gate stack is a P-type gate stack.

3 . The integrated circuit structure of claim 1 , wherein the well dopants are P-type dopants, and the gate stack is an N-type gate stack.

4 . The integrated circuit structure of claim 1 , wherein the pair of epitaxial source or drain structures is a pair of non-discrete epitaxial source or drain structures.

5 . The integrated circuit structure of claim 1 , wherein the well dopants are counter dopants.

6 . An integrated circuit structure, comprising:
a subfin structure; a non-conductive layer on the subfin structure, the non-conductive layer comprising silicon and carbon; a vertical arrangement of horizontal semiconductor nanowires over the non-conductive layer comprising silicon and carbon, the non-conductive layer comprising silicon and carbon vertically spaced apart from a bottommost nanowire of the vertical arrangement of horizontal semiconductor nanowires; a gate stack surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack in contact with the non-conductive layer comprising silicon and carbon; and a pair of epitaxial source or drain structures at first and second ends of the vertical arrangement of horizontal semiconductor nanowires.

7 . The integrated circuit structure of claim 6 , wherein the subfin structure comprises N-type dopants, and the gate stack is a P-type gate stack.

8 . The integrated circuit structure of claim 6 , wherein the subfin structure comprises P-type dopants, and the gate stack is an N-type gate stack.

9 . The integrated circuit structure of claim 6 , wherein the pair of epitaxial source or drain structures is a pair of non-discrete epitaxial source or drain structures.

10 . The integrated circuit structure of claim 6 , wherein the gate stack comprises a high-k gate dielectric layer and a metal gate electrode.

11 . A computing device, comprising:
a board; and a component coupled to the board, the component including an integrated circuit structure, comprising:
a subfin structure having well dopants with a concentration of greater than 3E18 atoms/cm 3 ;
a vertical arrangement of horizontal semiconductor nanowires over the subfin structure;
a silicon carbide dielectric structure vertically between the vertical arrangement of horizontal semiconductor nanowires and the subfin structure, the silicon carbide dielectric structure vertically spaced apart from a bottommost nanowire of the vertical arrangement of horizontal semiconductor nanowires;
a gate stack surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires, wherein the gate stack is in contact with the silicon carbide dielectric structure; and
a pair of epitaxial source or drain structures at first and second ends of the vertical arrangement of horizontal semiconductor nanowires.

12 . The computing device of claim 11 , further comprising:
a memory coupled to the board.

13 . The computing device of claim 11 , further comprising:
a communication chip coupled to the board.

14 . The computing device of claim 11 , wherein the component is a packaged integrated circuit die.

15 . The computing device of claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

16 . A computing device, comprising:
a board; and a component coupled to the board, the component including an integrated circuit structure, comprising:
a subfin structure;
a non-conductive layer on the subfin structure, the non-conductive layer comprising silicon and carbon;
a vertical arrangement of horizontal semiconductor nanowires over the non-conductive layer comprising silicon and carbon, the non-conductive layer comprising silicon and carbon vertically spaced apart from a bottommost nanowire of the vertical arrangement of horizontal semiconductor nanowires;
a gate stack surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack in contact with the non-conductive layer comprising silicon and carbon; and
a pair of epitaxial source or drain structures at first and second ends of the vertical arrangement of horizontal semiconductor nanowires.

17 . The computing device of claim 16 , further comprising:
a memory coupled to the board.

18 . The computing device of claim 16 , further comprising:
a communication chip coupled to the board.

19 . The computing device of claim 16 , wherein the component is a packaged integrated circuit die.

20 . The computing device of claim 16 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

Assignees

• Intel Corp

Inventors

• Cea Stephen M
• Lilak Aaron D
• Keys Patrick
• Weber Cory
• Mehandru Rishabh
• Murthy Anand S
• Guha Biswajeet
• Hasan Mohammad
• Hsu William
• Ghani Tahir
• Han Chang Wan
• Park Kihoon
• Omar Sabih

Classifications

• H10P14/3452

  Microstructure · CPC title

• H10W15/01

  Manufacture or treatment · CPC title

• H10W15/00

  Highly-doped buried regions of integrated devices · CPC title

• H10D62/118

  Nanostructure semiconductor bodies · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title