Semiconductor device

Patent metadata

Field	Value
Publication number	US-12575149-B2
Application number	US-202218067743-A
Country	US
Kind code	B2
Filing date	Dec 19, 2022
Priority date	Jan 25, 2021
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

Provided is a semiconductor device comprising a semiconductor substrate, the semiconductor substrate comprising an active portion, a second conductivity type circumferential well region surrounding the active portion in a top view, and a trench portion provided in the active portion on an upper surface of the semiconductor substrate, wherein the active portion includes a center portion including a first conductivity type emitter region, and a circumferential portion surrounding the center portion, wherein the center portion includes a second conductivity type active side bottom region provided across bottoms of at least two of the trench portion, the circumferential portion includes a second conductivity type circumferential side bottom region electrically connected to the circumferential well region, facing the active side bottom region, and provided at the bottom of the trench portion, and the active side bottom region and the circumferential side bottom region are provided apart from each other.

First claim

What is claimed is:

1 . A semiconductor device comprising a semiconductor substrate, the semiconductor substrate comprising:
an active portion; a circumferential well region of a second conductivity type surrounding the active portion in a top view; and a trench portion provided in the active portion on an upper surface of the semiconductor substrate, wherein the trench portion comprises a plurality of linear trench portions extending in parallel in an extending direction, wherein the plurality of linear trench portions are provided in a striped pattern in a top view, wherein each of the plurality of linear trench portions is spaced apart from its nearest neighboring one of the plurality of linear trench portions in an array direction, wherein each of the plurality of linear trench portions has a bottom, and wherein the active portion includes:
a center portion including an emitter region of a first conductivity type; and
a circumferential portion surrounding the center portion, wherein
the center portion includes an active side bottom region of the second conductivity type provided across and extending between the bottoms of at least two of the plurality of linear trench portions,
the circumferential portion includes a circumferential side bottom region of the second conductivity type that is electrically connected to the circumferential well region, faces the active side bottom region, has an upper surface, extends from the circumferential well region toward the active side bottom region, and is provided at the bottom of one or more of the plurality of linear trench portions,
the active side bottom region and the circumferential side bottom region are provided apart from each other in at least one of the array direction and the extending direction, and
an upper surface of the circumferential side bottom region is provided closer to a lower surface of the semiconductor substrate than the upper surface of the semiconductor substrate in a depth direction of the semiconductor substrate.

2 . The semiconductor device according to claim 1 , wherein
the active side bottom region is also provided in the circumferential portion.

3 . The semiconductor device according to claim 1 , wherein
the active side bottom region is electrically floating.

4 . The semiconductor device according to claim 1 , wherein
there is a boundary between the active portion and the well region, in a cross section in the extending direction through a portion of the semiconductor device where the boundary between the active portion and the well region is perpendicular to the extending direction, the active side bottom region and the circumferential side bottom region are provided apart from each other in the extending direction.

5 . The semiconductor device according to claim 1 , wherein
in a cross section in the array direction through a portion of the semiconductor device where the well region, the plurality of linear trench portions, and the circumferential portion extend in parallel in the extending direction, the active side bottom region and the circumferential side bottom region are provided apart from each other in the array direction, the circumferential side bottom region terminates at the bottom of one of the plurality of the linear trench portions in a direction toward the active side bottom region in the array direction.

6 . The semiconductor device according to claim 5 , wherein
in the cross section, the active side bottom region terminates at the bottom of another one of the plurality of linear trench portions.

7 . The semiconductor device according to claim 1 , wherein
impurity concentrations of the active side bottom region and the circumferential side bottom region are the same.

8 . The semiconductor device according to claim 1 , wherein
an impurity concentration of the circumferential side bottom region is larger than an impurity concentration of the active side bottom region.

9 . The semiconductor device according to claim 1 , wherein
an impurity concentration of the circumferential well region is larger than the impurity concentration of the circumferential side bottom region.

10 . The semiconductor device according to claim 1 , wherein
the active side bottom region and the circumferential side bottom region are provided at a same depth in a depth direction of the semiconductor substrate.

11 . The semiconductor device according to claim 1 , wherein
the circumferential side bottom region is provided wider than the active side bottom region in a depth direction of the semiconductor substrate.

12 . The semiconductor device according to claim 1 , wherein
a distance in the array direction of the plurality of linear trench portions of the active side bottom region and the circumferential side bottom region is a pitch width of the striped pattern of the plurality of linear trench portions or more and twenty times or less of the pitch width of the striped pattern of the plurality of linear trench portions.

13 . The semiconductor device according to claim 12 , wherein
the distance in the array direction of the active side bottom region and the circumferential side bottom region is 2 μm or more and 40 μm or less.

14 . The semiconductor device according to claim 1 , wherein the plurality of linear trench portions comprises:
a plurality of linear gate trench portions; and a plurality of linear dummy trench portions, wherein at least one of the plurality of linear gate trench portion is provided between the active side bottom region and the circumferential side bottom region in a depth direction of the semiconductor substrate.

15 . The semiconductor device according to claim 1 , wherein
the circumferential side bottom region is provided in a range that is five times or less a pitch width of the stripe pattern of the plurality of linear trench portions from the circumferential well region in the array direction of the plurality of linear trench portions.

16 . The semiconductor device according to claim 15 , wherein
a distance in the array direction of the active side bottom region and the circumferential side bottom region is larger than a width in which the circumferential side bottom region is provided.

17 . The semiconductor device according to claim 1 , further comprising:
a drift region of the first conductivity type; and a buffer region of the first conductivity type provided between the drift region and a lower surface of the semiconductor substrate, wherein the trench portion comprises at least one circumferential side deepening trench portion that is provided between the active side bottom region and the circumferential side bottom region in the array direction of the trench portion in the circumferential portion, and is formed deeper than the active side bottom region and the circumferential side bottom region, but does not reach the buffer region.

18 . The semiconductor device according to claim 17 , wherein
the trench portion comprises an active side deepening trench portion that is at least partially provided in the center portion, and is formed deeper than the active side bottom region.

19 . The semiconductor device according to claim 17 , wherein
the center portion comprises an active side bottomless region of the first conductivity type that is sandwiched by the active side bottom region in a top view, and is provided at a same depth as the active side bottom region in a depth direction of the semiconductor substrate.

20 . The semiconduc

Assignees

• Fuji Electric Co Ltd

Inventors

• Ozaki Daisuke
• Noguchi Seiji
• Sakurai Yosuke
• Hamasaki Ryutaro
• Yamada Takuya
• Ikura Yoshihiro

Classifications

• H10D62/127

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title

• H10D62/107

  Buried supplementary regions, e.g. buried guard rings  (multi-RESURF H10D62/111) · CPC title

• H10D12/481 Primary

  having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title

• H10D64/117

  Recessed field plates, e.g. trench field plates or buried field plates · CPC title