Semiconductor devices including gate-all-around type field effect transistor

Patent metadata

Field	Value
Publication number	US-12575135-B2
Application number	US-202318195749-A
Country	US
Kind code	B2
Filing date	May 10, 2023
Priority date	Aug 29, 2022
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

A semiconductor device includes a substrate including an active region extending in a first direction, a gate electrode layer crossing the active region and extending in a second direction, a plurality of channel layers on the active region, spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, and disposed sequentially from the active region, and surrounded by the gate electrode layer, gate spacer layers disposed on side surfaces of the gate electrode layer in the first direction, and source/drain regions disposed on the active region, on sides of the gate electrode layer, and connected to the plurality of channel layers. An uppermost channel layer among the plurality of channel layers includes channel portions separated from each other in the first direction and disposed below the gate spacer layers.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a substrate comprising an active region extending in a first direction; a gate electrode layer crossing the active region and extending in a second direction; a plurality of channel layers on the active region, spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, disposed sequentially from the active region, and surrounded by the gate electrode layer; gate spacer layers on side surfaces of the gate electrode layer in the first direction; and source/drain regions on the active region, on sides of the gate electrode layer, and connected to the plurality of channel layers, wherein an uppermost channel layer among the plurality of channel layers comprises channel portions separated from each other in the first direction and disposed below the gate spacer layers, and wherein the channel portions protrude toward the gate electrode layer.

2 . The semiconductor device of claim 1 , further comprising a gate dielectric layer between the plurality of channel layers and the gate electrode layer,
wherein the gate dielectric layer is disposed on inner side surfaces of the channel portions facing the gate electrode layer.

3 . The semiconductor device of claim 1 , further comprising inner spacer layers between the gate electrode layer and the source/drain regions, below the uppermost channel layer,
wherein at least a portion of lower surfaces of the channel portions contact the inner spacer layers.

4 . The semiconductor device of claim 1 , wherein the plurality of channel portions are located at substantially a same level as each other.

5 . The semiconductor device of claim 1 , wherein the gate electrode layer has a first length between the channel portions in the first direction, and a second length on an upper surface of a channel layer below the uppermost channel layer among the plurality of channel layers, and
wherein the second length is greater than the first length.

6 . The semiconductor device of claim 1 , wherein the gate electrode layer extends from above the uppermost channel layer to below the uppermost channel layer.

7 . The semiconductor device of claim 1 , wherein a level of a lower surface of an uppermost region of the gate electrode layer is lower than a level of upper surfaces of the source/drain regions.

8 . The semiconductor device of claim 1 , further comprising a cover insulating layer between lower surfaces of the gate spacer layers and the channel portions.

9 . The semiconductor device of claim 1 , wherein each of the channel portions comprises an upper region and a lower region below the upper region, and
the upper region and the lower region have different lengths.

10 . A semiconductor device comprising:
a substrate comprising a first active region extending in a first direction in a first region and a second active region extending in the first direction in a second region; a first gate structure, crossing the first active region, on the first region, and extending in a second direction; a second gate structure crossing the second active region, on the second region, and extending in the second direction; a first channel layer, a second channel layer and a third channel layer on the first active region, spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, disposed sequentially from the first active region, and surrounded by the first gate structure; a fourth channel layer, a fifth channel layer and a sixth channel layer on the second active region, spaced apart from each other in the third direction and disposed sequentially from the second active region, and surrounded by the second gate structure; first source/drain regions on sides of the first gate structure, on the first active region and connected to the first, the second, and the third channel layers; and second source/drain regions on sides of the second gate structure, on the second active region and connected to the fourth, the fifth, and the sixth channel layers, wherein a germanium (Ge) concentration of the first source/drain regions is higher than a germanium (Ge) concentration of the second source/drain regions, and wherein the third channel layer comprises channel portions spaced apart from each other in the first direction below the first gate structure.

11 . The semiconductor device of claim 10 , wherein the sixth channel layer is disposed below the second gate structure as a single layer extending in the first direction.

12 . The semiconductor device of claim 10 , further comprising:
first contact plugs connected to the first source/drain regions; and second contact plugs connected to the second source/drain regions, wherein the first contact plugs recess the first source/drain regions from upper surfaces of the first source/drain regions to a first depth, and the second contact plugs recess the second source/drain regions from upper surfaces of the second source/drain regions to a second depth different from the first depth.

13 . The semiconductor device of claim 12 , wherein the first depth is greater than the second depth.

14 . A semiconductor device comprising:
a substrate comprising an active region extending in a first direction; a gate structure on the substrate, crossing the active region and extending in a second direction; and a first channel layer, a second channel layer and a third channel layer on the active region, spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, and disposed sequentially from the active region and surrounded by the gate structure, wherein the third channel layer comprises channel portions respectively disposed below end portions of the gate structure in the first direction, wherein the gate structure has a first length between the channel portions in the first direction and a second length on an upper surface of the second channel layer, and wherein the second length is different than the first length.

15 . The semiconductor device of claim 14 , wherein the channel portions are located outside of a vertical central axis of the gate structure in the first direction.

16 . The semiconductor device of claim 14 , wherein each of the channel portions has a length in the first direction that is less than half of a length of the first channel layer in the first direction and less than half of a length of the second channel layer in the first direction.

17 . The semiconductor device of claim 14 , wherein the gate structure is provided on opposite side surfaces of the channel portions and extends between the side surfaces.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Younggwon
• Kang Myunggil
• Kim Dongwon
• Park Beomjin
• Jeon Inu
• Jeong Soojin

Classifications

• H10D64/258

  characterised by the relative positions of the source or drain electrodes with respect to the gate electrode · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/121 Primary

  oriented parallel to substrates · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title