Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10204902-B2
Application number	US-201615295115-A
Country	US
Kind code	B2
Filing date	Oct 17, 2016
Priority date	Feb 26, 2016
Publication date	Feb 12, 2019
Grant date	Feb 12, 2019

Abstract

A semiconductor device includes a first active structure on a substrate including a first epitaxial pattern, a second epitaxial pattern and a first channel pattern between the first epitaxial pattern and the second epitaxial pattern, the first channel pattern including at least one channel pattern stacked on the substrate. A first gate structure is disposed on top and bottom surfaces of the first channel pattern. A second active structure on the substrate and includes the second epitaxial pattern, a third epitaxial pattern and a second channel pattern between the second epitaxial pattern and the third epitaxial pattern in the first direction. The second channel pattern includes at least one channel pattern stacked on the substrate. The number of stacked second channel patterns is greater than the number of stacked first channel patterns. A second gate structure is disposed on top and bottom surfaces of the second channel pattern.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first active structure on a substrate and including a first epitaxial pattern, a second epitaxial pattern and a first channel pattern between the first epitaxial pattern and the second epitaxial pattern in a first direction parallel to a top surface of the substrate, the first channel pattern including at least one channel pattern stacked on the substrate;
a first gate structure disposed on top and bottom surfaces of the first channel pattern and extending in a second direction perpendicular to the first direction and parallel to the top surface of the substrate;
a second active structure on the substrate and including the second epitaxial pattern, a third epitaxial pattern and a second channel pattern between the second epitaxial pattern and the third epitaxial pattern in the first direction, the second channel pattern including at least two channel patterns stacked on the substrate, wherein the number of stacked second channel patterns is greater than the number of stacked first channel patterns; and
a second gate structure disposed on top and bottom surfaces of the second channel pattern and extending in the second direction,
wherein the second epitaxial pattern is commonly used by the first and second active structures, and
wherein the second epitaxial pattern is disposed between the first channel pattern and the second channel pattern in the first direction.

2. The semiconductor device according to claim 1 , wherein opposite ends of the first channel pattern respectively contact the first epitaxial pattern and the second epitaxial pattern, and the first channel pattern includes a plurality of channel patterns that are spaced apart from each other in a third direction perpendicular to the top surface of the substrate, and
wherein opposite ends of the second channel pattern respectively contact the second epitaxial pattern and the third epitaxial pattern, and the second channel pattern includes a plurality of channel patterns that are spaced apart from each other in the third direction.

3. The semiconductor device according to claim 2 , further comprising first spacers on sidewalls of the first and second gate structures that are positioned on uppermost ones of the first and second channel patterns.

4. The semiconductor device according to claim 2 , further comprising second spacers between the first and second epitaxial patterns and the first gate structure and between the second and third epitaxial patterns and the second gate structure, the second spacers each including an insulating material.

5. The semiconductor device according to claim 1 , wherein the first gate structure includes a first gate insulating pattern, a first gate electrode and a first hard mask, and the second gate structure includes a second gate insulating pattern, a second gate electrode and a second hard mask.

6. The semiconductor device according to claim 5 , further comprising:
an insulating interlayer covering upper portions of the first and second active structures and upper portions of the first and second gate structures; and
a first contact plug, a second contact plug and a third contact plug that penetrate the insulating interlayer and contact the first epitaxial pattern, the second epitaxial pattern and the third epitaxial pattern, respectively.

7. The semiconductor device according to claim 1 , wherein the first epitaxial pattern and the second epitaxial pattern extend in the second direction, and wherein the first channel pattern and the second channel pattern each include a plurality of channel patterns arranged in the second direction.

8. The semiconductor device according to claim 1 , wherein the first channel pattern and the second channel pattern have substantially a same thickness in a third direction perpendicular to the top surface of the substrate.

9. The semiconductor device according to claim 1 , wherein the first channel pattern and the second channel pattern each include a plurality of channel patterns, and
wherein at least one of the plurality of first channel patterns has a different thickness from a thickness of at least one of the plurality of second channel patterns in a third direction perpendicular to the top surface of the substrate.

10. The semiconductor device according to claim 1 , wherein the first channel pattern and the second channel pattern each include a plurality of channel patterns, wherein the plurality of first channel patterns each have substantially a same thickness in a third direction perpendicular to the top surface of the substrate, and wherein at least one of the plurality of second channel patterns has a different thickness from a thickness of another channel pattern of the plurality of second channel patterns in the third direction.

11. The semiconductor device according to claim 10 , wherein an uppermost one of the plurality of second channel patterns has a different thickness from a thickness of another channel pattern of the plurality of second channel patterns under the uppermost one of the plurality of second channel patterns in the third direction.

12. The semiconductor device according to claim 1 , wherein a side surface of the first channel pattern facing the second channel pattern is in direct contact with the second epitaxial pattern and wherein a side surface of the second channel pattern facing the first channel pattern is in direct contact with the second epitaxial pattern.

13. A semiconductor device, comprising:
a first active structure on a substrate and including a first epitaxial pattern, a second epitaxial pattern and a first channel pattern between the first epitaxial pattern and the second epitaxial pattern in a first direction parallel to a top surface of the substrate, the first channel pattern including at least one channel pattern stacked on the substrate, wherein a first side surface of the first channel pattern faces a side surface of the first epitaxial pattern along the first direction, and wherein a second side surface of the first channel pattern faces a side surface of the second epitaxial pattern along the first direction;
a first gate structure disposed on top and bottom surfaces of the first channel pattern and extending in a second direction perpendicular to the first direction and parallel to the top surface of the substrate;
a second active structure on the substrate and including a third epitaxial pattern, a fourth epitaxial pattern and a second channel pattern between the third epitaxial pattern and the fourth epitaxial pattern in the first direction, the second channel pattern including at least one channel pattern stacked on the substrate, wherein the number of stacked second channel patterns is greater than the number of stacked first channel patterns, and wherein the second and third epitaxial patterns are disposed between the first channel pattern and the second channel pattern;
a second gate structure disposed on top and bottom surfaces of the second channel pattern and extending in the second direction;
a dummy active structure on the substrate, the dummy active structure including the second epitaxial pattern, the third epitaxial pattern, a dummy channel pattern between the second epitaxial pattern and the third epitaxial pattern in the first direction, the dummy channel pattern including at least one channel pattern stacked on the substrate; and
a dummy gate structure disposed on top and bottom surfaces of the dummy channel pattern and extending in the second direction.

14. The semiconductor device according to claim 13 , wherein the dummy active structure has a same shape as a shape of the firs

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Hae-Wang

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L21/823412

  Electricity · mapped topic

• H01L29/7831

  Electricity · mapped topic

• H01L29/42356

  Electricity · mapped topic

• H01L29/6656

  Electricity · mapped topic