Semiconductor structure and processor

Patent metadata

Field	Value
Publication number	US-12575091-B2
Application number	US-202217954639-A
Country	US
Kind code	B2
Filing date	Sep 28, 2022
Priority date	Feb 28, 2022
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

A semiconductor structure and a memory are provided The semiconductor structure includes: a first active area pattern; a first gate pattern, a second gate pattern, a third gate pattern and a fourth gate pattern which are arranged at intervals in a first direction; a first connection pattern, arranged to connect the second gate pattern and the third gate pattern in parallel; a second connection pattern, arranged to connect the first gate pattern and the fourth gate pattern in parallel; at least two first contact hole patterns arranged in parallel; and at least two second contact hole patterns and at least two third contact hole patterns arranged in parallel.

First claim

What is claimed is:

1 . A semiconductor structure, comprising:
a first active area pattern; a first gate pattern, a second gate pattern, a third gate pattern, and a fourth gate pattern which are arranged at intervals in a first direction, each of the first gate pattern, the second gate pattern, the third gate pattern, and the fourth gate pattern extending in a second direction, and overlapping with the first active area pattern; a first connection pattern, arranged to connect the second gate pattern and the third gate pattern in parallel; a second connection pattern, arranged to connect the first gate pattern and the fourth gate pattern in parallel; at least two first contact hole patterns arranged in parallel, arranged on a side, away from the second gate pattern, of the first gate pattern, and each of the first contact hole patterns overlapping with the first active area pattern; at least two second contact hole patterns arranged in parallel, arranged between the second gate pattern and the third gate pattern, and each of the second contact hole patterns overlapping with the first active area pattern; at least two third contact hole patterns arranged in parallel, arranged on a side, away from the third gate pattern, of the fourth gate pattern, and each of the third contact hole patterns overlapping with the first active area pattern; at least two fourth contact hole patterns arranged in parallel, wherein the at least two fourth contact hole patterns overlap with the first connection pattern; wherein one of the at least two fourth contact hole patterns is arranged at the overlap regions between the first connection pattern and the second gate pattern to connect the first connection pattern to the second gate pattern, and the other of the at least two fourth contact hole patterns is arranged at the overlap regions between the first connection pattern and the third gate pattern to connect the first connection pattern to the third gate pattern; and at least two fifth contact hole patterns arranged in parallel, wherein the at least two fifth contact hole patterns overlap with the second connection pattern; wherein one of the at least two fifth contact hole patterns is arranged at the overlap regions between the second connection pattern and the first gate pattern to connect the second connection pattern to the first gate pattern, and the other of the at least two fifth contact hole patterns is arranged at the overlap regions between the second connection pattern and the fourth gate pattern to connect the second connection pattern to the fourth gate pattern.

2 . The semiconductor structure of claim 1 , wherein the first contact hole patterns, the second contact hole patterns, and the third contact hole patterns are all arranged at intervals in the second direction.

3 . The semiconductor structure of claim 1 , wherein in the second direction, the first connection pattern and the second connection pattern are arranged on both sides of the first active area pattern, respectively.

4 . The semiconductor structure of claim 1 , further comprising:
a second active area pattern, arranged at an interval with the first active area pattern in the second direction; and a fifth gate pattern and a sixth gate pattern which are arranged at an interval in the first direction, each of the fifth gate pattern and the sixth gate pattern extending in the second direction, and overlapping with the second active area pattern, wherein the second connection pattern is further arranged to connect the fifth gate pattern and the sixth gate pattern in parallel.

5 . The semiconductor structure of claim 4 , wherein in the second direction, the third gate pattern and the fifth gate pattern are arranged at an interval, and the fourth gate pattern and the sixth gate pattern are arranged at an interval.

6 . The semiconductor structure of claim 5 , further comprising:
at least two sixth contact hole patterns arranged in parallel, arranged on a side, away from the sixth gate pattern, of the fifth gate pattern, and overlapping with the second active area pattern; at least two seventh contact hole patterns arranged in parallel, arranged between the fifth gate pattern and the sixth gate pattern, and overlapping with the second active area pattern; and at least two eighth contact hole patterns arranged in parallel, arranged on a side, away from the fifth gate pattern, of the sixth gate pattern, and overlapping with the second active area pattern.

7 . The semiconductor structure of claim 6 , wherein the sixth contact hole patterns are arranged at an interval in the second direction, the seventh contact hole patterns are arranged at an interval in the second direction, and the eighth contact hole patterns are arranged at an interval in the second direction; and
wherein in the second direction, the sixth contact hole patterns and the seventh contact hole patterns are arranged in a staggered manner at a set distance, and the seventh contact hole patterns and the eighth contact hole patterns are arranged in a staggered manner at a set distance.

8 . The semiconductor structure of claim 4 , further comprising:
a seventh gate pattern and an eighth gate pattern which are arranged at an interval in the first direction, each of the seventh gate pattern and the eighth gate pattern extending in the second direction, and overlapping with the second active area pattern, and in the second direction, the first gate pattern and the seventh gate pattern being arranged at an interval, and the second gate pattern and the eighth gate pattern being arranged at an interval; a third connection pattern, connected to the seventh gate pattern; and a fourth connection pattern, connected to the eighth gate pattern.

9 . The semiconductor structure of claim 8 , further comprising:
at least two ninth contact hole patterns arranged in parallel, arranged on a side, away from the eighth gate pattern, of the seventh gate pattern, and overlapping with the second active area pattern; and at least two tenth contact hole patterns arranged in parallel, arranged between the seventh gate pattern and the eighth gate pattern, and overlapping with the second active area pattern.

10 . The semiconductor structure of claim 8 , further comprising:
a third active area pattern, arranged at an interval with the second active area pattern in the second direction; a ninth gate pattern, a tenth gate pattern, an eleventh gate pattern, and a twelfth gate pattern which are arranged at intervals in the first direction, each of the ninth gate pattern, the tenth gate pattern, the eleventh gate pattern, and the twelfth gate pattern extending in the second direction, and overlapping with the third active area pattern, wherein the fourth connection pattern is further arranged to connect the ninth gate pattern, the tenth gate pattern, the eleventh gate pattern, and the twelfth gate pattern in parallel.

11 . The semiconductor structure of claim 10 , further comprising:
at least one eleventh contact hole pattern, arranged on a side, away from the tenth gate pattern, of the ninth gate pattern, and overlapping with the third active area pattern; at least two twelfth contact hole patterns arranged in parallel, arranged between the ninth gate pattern and the tenth gate pattern, and overlapping with the third active area pattern; at least one thirteenth contact hole pattern, arranged between the tenth gate pattern and the eleventh gate pattern, and overlapping with the third active area pattern; at least two fourteenth contact hole patterns arranged in parallel, arranged between the eleventh gate pattern and the twelfth gate pattern, and overlapping with the third

Assignees

• Changxin Memory Tech Inc

Inventors

• Li Minghao
• Zhang Fengqin
• Shang Weibing

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10B12/09

  with simultaneous manufacture of the peripheral circuit region and memory cells · CPC title

• H10B12/01

  Manufacture or treatment · CPC title

• H10D30/01

  Manufacture or treatment · CPC title

• H10D10/01

  Manufacture or treatment · CPC title