Embedded photonic integrated circuits

Patent metadata

Field	Value
Publication number	US-12571959-B2
Application number	US-202318130052-A
Country	US
Kind code	B2
Filing date	Apr 3, 2023
Priority date	Apr 3, 2023
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

A substrate for a multi-chip package includes at least one photonic integrated circuit (PIC) interposer mounted in a cavity in a first major surface. Each PIC interposer is configured to electrically connect with, or optically couple to, a plurality of integrated circuit devices. The substrate further includes at least one optical coupler that is optically coupled to the PIC interposer.

First claim

We claim:

1 . A substrate for a multi-chip package, the substrate comprising:
a first major surface and an opposed second major surface; at least one photonic integrated circuit (PIC) interposer mounted in a cavity in the first major surface of the substrate, wherein each PIC interposer is configured to electrically connect with, or optically couple to, a plurality of integrated circuit devices; at least one optical coupler in the substrate, wherein the at least one optical coupler is optically coupled to the at least one PIC interposer; a central region comprising a plurality of cavities each housing a PIC interposer in the plurality of PIC interposers; and a peripheral region outboard of the central region, wherein the peripheral region comprises a plurality of vias extending along a direction substantially normal to a plane of the first major surface of the substrate.

2 . The substrate of claim 1 , wherein the substrate comprises glass, and the optical coupler comprises an optical waveguide in the substrate.

3 . The substrate of claim 1 , wherein the substrate comprises an organic material, and the optical coupler comprises an on-cavity PIC (OCPIC).

4 . The substrate of claim 1 , wherein the substrate comprises a plurality of PIC interposers, and adjacent PIC interposers in the plurality of PIC interposers are optically coupled via edge couplers.

5 . The substrate of claim 1 , wherein each PIC interposer comprises a mounting surface configured to mount thereon a plurality of integrated circuit devices.

6 . The substrate of claim 1 , wherein the substrate comprises a plurality of optical waveguides optically coupling the plurality of PIC interposers, the optical waveguides extending along a direction substantially parallel to the plane of the first major surface of the substrate.

7 . The substrate of claim 1 , wherein the second major surface of the substrate comprises an array of solder bumps configured for mounting the substrate to an electronic component.

8 . A mounting substrate for a multi-chip package, the substrate comprising:
a first major surface and an opposed second major surface, wherein the first major surface of the substrate comprises a plurality of cavities; at least one PIC interposer in each cavity of the plurality of cavities, wherein each PIC interposer is configured to electrically connect to or optically couple with at least four integrated circuit devices; and a plurality of optical couplers each extending along a direction substantially parallel to a plane of the first major surface of the substrate, and wherein the plurality of optical couplers optically interconnect the PIC interposers in the plurality of cavities, wherein the substrate comprises glass, and the optical couplers comprise optical waveguides in the substrate.

9 . The mounting substrate of claim 8 , wherein the optical couplers are chosen from on-cavity PICs (OCPIC), optical waveguides, and edge couplers.

10 . The mounting substrate of claim 8 , wherein at least some of the optical waveguides terminate at an edge of the substrate to provide optical coupling to another multi-chip package.

11 . A system, comprising:
a plurality of multi-chip packages, wherein each multi-chip package comprises:
a glass substrate having a first major surface and an opposed second major surface, wherein the first major surface of the substrate comprises a plurality of cavities;
at least one PIC interposer in each cavity of the plurality of cavities;
a plurality of integrated circuit devices mounted on the first major surface of the substrate, wherein each PIC interposer is electrically connected with, or optically coupled to, at least four integrated circuit devices;
optical couplers optically coupling the PIC interposers, wherein at least a portion of the optical couplers have an output at an edge of the substrate; and
a plurality of electrically conductive vias extending through the substrate along a direction substantially normal to a plane of the first major surface of the substrate; and
optical fibers optically coupled to the output of the optical couplers to transmit optical data between the plurality of multi-chip packages.

12 . The system of claim 11 , wherein the plurality of PIC interposers are mounted in a central region of the substrate, and at least some of the electrically conductive vias are in a peripheral region of the substrate outboard of the central region.

13 . The system of claim 11 , wherein the optical couplers each comprise optical waveguides in the substrate.

14 . The system of claim 11 , wherein a first PIC interposer in a first multi-chip package is optically coupled to a second PIC interposer in a second multi-chip package via vertical optical coupling.

Assignees

• Intel Corp

Inventors

• Hosseini Kaveh
• Mahajan Ravindranath V
• Chiu Chia-Pin

Classifications

• G02B6/4274

  Electrical aspects (G02B6/4263 and G02B6/4265 take precedence) · CPC title

• G02B6/43

  Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections · CPC title

• G02B6/12004 Primary

  Combinations of two or more optical elements · CPC title