Electronic device having diplexer of stacked structure

Patent metadata

Field	Value
Publication number	US-12567877-B2
Application number	US-202318185063-A
Country	US
Kind code	B2
Filing date	Mar 16, 2023
Priority date	Sep 17, 2020
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

An electronic device is provided. The electronic device includes an antenna, a wireless communication circuit, and a diplexer. The diplexer includes a first port, and second and third ports connected to the wireless communication circuit, a low pass filter (LPF) configured to filter an RF signal of a low frequency band from a signal received from one of the first port and the second port and output same to the other one of the first port and the second port, and a high pass filter (HPF) configured to filter an RF signal of a high frequency band from a signal received from one of the first port and the third port and output same to the other one of the first port and the third port.

First claim

What is claimed is:

1 . An electronic device comprising:
an antenna; a wireless communication circuit; and a diplexer connected to the antenna and the wireless communication circuit, wherein the diplexer comprises:
a first port connected to the antenna,
a second port connected to the wireless communication circuit,
a third port connected to the wireless communication circuit,
a low pass filter (LPF) configured to filter a signal received from one of the first port and the second port so as to obtain an RF signal of a low-frequency band and to output the RF signal of the low-frequency band to the other port between the first port and the second port,
a high pass filter (HPF) configured to filter a signal received from one of the first port and the third port so as to obtain an RF signal of a high-frequency band and to output the RF signal of the high-frequency band to the other port between the first port and the third port, and
a ground structure connected to the LPF and the HPF,
wherein the LPF comprises a capacitor disposed on an outer surface of a printed circuit board (PCB) and an inductor formed in a pattern within the PCB, wherein the HPF comprises an inductor disposed on the surface of the PCB and a capacitor formed in a pattern on the PCB, wherein the PCB comprises a plurality of layers, wherein the ground structure surrounds the LPF and the HPF along a direction in which the plurality of layers is stacked, and wherein the first port, the second port, and the third port are disposed on the outer surface of the PCB.

2 . The electronic device of claim 1 ,
wherein the LPF comprises an LPF capacitor (LC) 2 , an LC 3 , an LPF inductor (LL) 1 , and an LL 2 , and the HPF comprises a HPF capacitor (HC) 1 , an HC 2 , an HC 3 , and an HPF inductor (HL) 1 , wherein one end of the LL 1 is connected to the first port and the other end of the LL 1 is connected to one end of the LL 2 , wherein the other end of the LL 2 is connected to the second port and one end of the LC 2 is connected to one end of the LL 2 and the other end of the LC 2 is connected to the other end of the LL 2 , wherein one end of the LC 3 is connected to the other end of the LL 1 and one end of the LL 2 , and the other end of the LC 3 is connected to the ground structure, wherein one end of the HC 1 is connected to the first port and the other end of the HC 1 is connected to one end of the HC 2 , wherein the other end of the HC 2 is connected to the third port, wherein one end of the HC 3 is connected to one end of the HC 1 and the other end of the HC 3 is connected to the other end of the HC 2 , wherein one end of the HL 1 is connected to the other end of the HC 1 and one end of the HC 2 , wherein the other end of the HL 1 is connected to the ground structure, wherein the LC 2 , the LC 3 , and the HL 1 are lumped elements disposed on the surface of the PCB, wherein the LL 1 , the LL 2 , the HC 1 , and the HC 2 are formed in a pattern on the PCB, and wherein the HC 3 is a lumped element disposed on the surface of the PCB or is formed in a pattern on the PCB.

3 . The electronic device of claim 2 ,
wherein the HC 3 is a lumped element disposed on the surface of the PCB, and wherein the PCB comprises: a first layer that includes the surface of the PCB, and in which pads for disposing a lumped element, a first part of the HC 1 , and a first part of the HC 2 are formed, a second layer that is disposed under the first layer, and in which a first part of the LL 1 , a first part of the LL 2 , a second part of the HC 1 , and a second part of the HC 2 are formed, and a third layer that is disposed under the second layer, and in which a second part of the LL 1 , a second part of the LL 2 , a third part of the HC 1 , and a third part of the HC 2 are formed.

4 . The electronic device of claim 3 , wherein the PCB further comprises a shielding sheet disposed under the third layer.

5 . The electronic device of claim 3 , wherein the ground structure comprises a plurality of ground patterns, the plurality of ground patterns comprising:
a first ground pattern provided in the first layer, the first ground pattern enclosing the pads, the first part of the HC 1 , and the first part of the HC 2 ; a second ground pattern provided in the second layer, the second ground pattern enclosing the first part of the LL 1 , the first part of the LL 2 , the second part of the HC 1 , and the second part of the HC 2 ; and a third ground pattern provided in the third layer, the third ground pattern enclosing the second part of the LL 1 , the second part of the LL 2 , the third part of the HC 1 , and the third part of the HC 2 .

6 . The electronic device of claim 5 , wherein a pad to which the other end of the LC 3 is attached among the pads is configured as a part of the first ground pattern.

7 . The electronic device of claim 5 , wherein the plurality of ground patterns are aligned and a plurality of vias that connect the plurality of ground patterns are formed along edges of the plurality of ground patterns.

8 . The electronic device of claim 2 ,
wherein the HC 3 is formed in a pattern on the PCB, and wherein the PCB comprises: a first layer that includes the surface of the PCB, and in which pads for disposing a lumped element are formed; a second layer located under the first layer, and in which a first part of the LL 1 and a first part of the LL 2 are formed; a third layer located under the second layer, and in which a second part of the LL 1 and a second part of the LL 2 are formed, formed; a fourth layer located under the third layer and including a shielding sheet; a fifth layer located under the fourth layer, and in which a first part of the HC 1 and a first part of the HC 2 are formed; a sixth layer located under the fifth layer, and in which a second part of the HC 1 and a second part of the HC 2 are formed; a seventh layer located under the sixth layer, and in which a third part of the HC 1 and a third part of the HC 2 are formed; an eighth layer located under the seventh layer, and in which a first part of the HC 3 is formed; and a ninth layer located under the eighth layer, and in which a second part of the HC 3 is formed.

9 . The electronic device of claim 8 , wherein the ground structure comprises a plurality of ground patterns, the plurality of ground patterns comprising:
a first ground pattern provided in the first layer, the first ground pattern enclosing the pads; a second ground pattern provided in the second layer, the second ground pattern enclosing the first part of the LL 1 and the first part of the LL 2 ; a third ground pattern provided in the third layer, the third ground pattern enclosing the second part of the LL 1 and the second part of the LL 2 ; a fourth ground pattern including the shielding sheet, the fourth ground pattern formed in the fourth layer; a fifth ground pattern provided in the fifth layer, the fifth ground pattern enclosing the first part of the HC 1 and the first part of the HC 2 ; a sixth ground pattern provided in the sixth layer, the sixth ground pattern enclosing the second part of the HC 1 and the second part of the HC 2 ; a seventh ground pattern provided in the seventh layer, the seventh ground pattern enclosing the third part of the HC 1 and the third part of the HC 2 ; an eighth ground pattern provided in the eighth layer, the eighth ground pattern enclosing the first part of the HC 3 ; and a ninth ground pattern provided in the ninth layer, the ninth ground pattern enclosing the second part of the HC 3 .

10 . The electronic device of claim 9 ,
wherein a pad to which the other end of the LC

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Jonghyun
• Kim Taeyoung
• Yang Dongil
• Na Hyoseok

Classifications

• H04B1/50

  using different frequencies for the two directions of communication · CPC title

• H03H7/0115

  comprising only inductors and capacitors (H03H7/075, H03H7/09, H03H7/12, H03H7/13 take precedence) · CPC title

• H01P1/213 Primary

  combining or separating two or more different frequencies (H01P1/215 takes precedence) · CPC title

• H04B1/48 Primary

  in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter {(H04B1/46 takes precedence)} · CPC title

• H04B1/0057

  using diplexing or multiplexing filters for selecting the desired band · CPC title